Edson I. Moreno

According to our database, Edson I. Moreno authored at least 13 papers between 2003 and 2014.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2014

MoNoC: A monitored network on chip with path adaptation mechanism.

Edson I. Moreno, Thais Webber, César A. M. Marcon, Fernando Gehm Moraes, Ney Laert Vilar Calazans

J. Syst. Archit., 2014

A monitored NoC with runtime path adaptation.

Edson I. Moreno, Thais Webber, César A. M. Marcon, Fernando Moraes, Ney Calazans

Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

2013

Determining the test sources/sinks for NoC TAMs.

Alexandre M. Amory, Edson I. Moreno, Fernando Moraes, Marcelo Lubaszewski

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2013

2012

Topological impact on latency and throughput: 2D versus 3D NoC comparison.

Yan Ghidini, Thais Webber, Edson I. Moreno, Ivan Quadros, Rubem Dutra Ribeiro Fagundes, César A. M. Marcon

Proceedings of the 25th Symposium on Integrated Circuits and Systems Design, 2012

Buffer depth and traffic influence on 3D NoCs performance.

Yan Ghidini, Thais Webber, Edson I. Moreno, Fernando Grando, Rubem Dutra Ribeiro Fagundes, César A. M. Marcon

Proceedings of the 23rd IEEE International Symposium on Rapid System Prototyping, 2012

2011

CAFES: A framework for intrachip application modeling and communication architecture design.

César A. M. Marcon, Ney Calazans, Edson I. Moreno, Fernando Moraes, Fabiano Hessel, Altamiro Amadeu Susin

J. Parallel Distributed Comput., 2011

Arbitration and routing impact on NoC design.

Edson I. Moreno, César A. M. Marcon, Ney Laert Vilar Calazans, Fernando Gehm Moraes

Proceedings of the 22nd IEEE International Symposium on Rapid System Prototyping, 2011

2010

Mapeamento e adaptação de rotas de comunicação em redes em chip.

Edson Ifarraguirre Moreno

PhD thesis, 2010

2008

Comparison of network-on-chip mapping algorithms targeting low energy consumption.

César Augusto Missio Marcon, Edson Ifarraguirre Moreno, Ney Laert Vilar Calazans, Fernando Gehm Moraes

IET Comput. Digit. Tech., 2008

Integrating Abstract NoC Models within MPSoC Design.

Edson Ifarraguirre Moreno, Katalin Maria Popovici, Ney Laert Vilar Calazans, Ahmed Amine Jerraya

Proceedings of the 19th IEEE/IFIP International Symposium on Rapid System Prototyping: RSP 2009, 2008

2007

Evaluation of Algorithms for Low Energy Mapping onto NoCs.

César A. M. Marcon, Edson I. Moreno, Ney Laert Vilar Calazans, Fernando Gehm Moraes

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

2005

Test Time Reduction Reusing Multiple Processors in a Network-on-Chip Based Architecture.

Alexandre M. Amory, Marcelo Lubaszewski, Fernando Gehm Moraes, Edson I. Moreno

Proceedings of the 2005 Design, 2005

2003

From VHDL Register Transfer Level to SystemC Transaction Level Modeling: A Comparative Case Study.

Ney Laert Vilar Calazans, Edson I. Moreno, Fabiano Hessel, Vitor M. da Rosa, Fernando Moraes, Everton Carara

Proceedings of the 16th Annual Symposium on Integrated Circuits and Systems Design, 2003