Fernando Latorre

According to our database1, Fernando Latorre authored at least 12 papers between 2002 and 2012.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Links

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Bibliography

2012
DDGacc: boosting dynamic DDG-based binary optimizations through specialized hardware support.
Proceedings of the 8th International Conference on Virtual Execution Environments, 2012

2011
CROB: Implementing a Large Instruction Window through Compression.
Trans. High Perform. Embed. Archit. Compil., 2011

Fg-STP: Fine-Grain Single Thread Partitioning on Multicores.
Proceedings of the 17th International Conference on High-Performance Computer Architecture (HPCA-17 2011), 2011

2010
Processor Microarchitecture: An Implementation Perspective
Synthesis Lectures on Computer Architecture, Morgan & Claypool Publishers, ISBN: 978-3-031-01729-2, 2010

2009
Boosting single-thread performance in multi-core systems through fine-grain multi-threading.
Proceedings of the 36th International Symposium on Computer Architecture (ISCA 2009), 2009

P-slice based efficient speculative multithreading.
Proceedings of the 16th International Conference on High Performance Computing, 2009

Anaphase: A Fine-Grain Thread Decomposition Scheme for Speculative Multithreading.
Proceedings of the PACT 2009, 2009

2008
Efficient resources assignment schemes for clustered multithreaded processors.
Proceedings of the 22nd IEEE International Symposium on Parallel and Distributed Processing, 2008

2007
Building a large instruction window through ROB compression.
Proceedings of the 2007 workshop on MEmory performance, 2007

2004
Cache organizations for clustered microarchitectures.
Proceedings of the 3rd Workshop on Memory Performance Issues, 2004

Back-end assignment schemes for clustered multithreaded processors.
Proceedings of the 18th Annual International Conference on Supercomputing, 2004

2002
Errata on "Measuring Experimental Error in Microprocessor Simulation".
SIGARCH Comput. Archit. News, 2002


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