Enric Gibert

According to our database1, Enric Gibert authored at least 20 papers between 2002 and 2017.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2017
HW/SW co-designed processors: Challenges, design choices and a simulation infrastructure for evaluation.
Proceedings of the 2017 IEEE International Symposium on Performance Analysis of Systems and Software, 2017

2016
Development and validation of hydrophobic molecular fields derived from the quantum mechanical IEF/PCM-MST solvation models in 3D-QSAR.
Journal of Computational Chemistry, 2016

Quantitative characterization of the software layer of a HW/SW co-designed processor.
Proceedings of the 2016 IEEE International Symposium on Workload Characterization, 2016

2015
Profiling Support for Runtime Managed Code: Next Generation Performance Monitoring Units.
Computer Architecture Letters, 2015

2014
Warm-Up Simulation Methodology for HW/SW Co-Designed Processors.
Proceedings of the 12th Annual IEEE/ACM International Symposium on Code Generation and Optimization, 2014

Accurate off-line phase classification for HW/SW co-designed processors.
Proceedings of the Computing Frontiers Conference, CF'14, 2014

Speculative hardware/software co-designed floating-point multiply-add fusion.
Proceedings of the Architectural Support for Programming Languages and Operating Systems, 2014

2013
Performance analysis and predictability of the software layer in dynamic binary translators/optimizers.
Proceedings of the Computing Frontiers Conference, 2013

2012
DDGacc: boosting dynamic DDG-based binary optimizations through specialized hardware support.
Proceedings of the 8th International Conference on Virtual Execution Environments, 2012

2011
Global productiveness propagation: a code optimization technique to speculatively prune useless narrow computations.
Proceedings of the ACM SIGPLAN/SIGBED 2011 conference on Languages, 2011

2009
Boosting single-thread performance in multi-core systems through fine-grain multi-threading.
Proceedings of the 36th International Symposium on Computer Architecture (ISCA 2009), 2009

Anaphase: A Fine-Grain Thread Decomposition Scheme for Speculative Multithreading.
Proceedings of the PACT 2009, 2009

2006
A dynamically reconfigurable cache for multithreaded processors.
J. Embedded Computing, 2006

Instruction scheduling for a clustered VLIW processor with a word-interleaved cache.
Concurrency and Computation: Practice and Experience, 2006

2005
Distributed Data Cache Designs for Clustered VLIW Processors.
IEEE Trans. Computers, 2005

Variable-Based Multi-module Data Caches for Clustered VLIW Processors.
Proceedings of the 14th International Conference on Parallel Architectures and Compilation Techniques (PACT 2005), 2005

2003
Flexible Compiler-Managed L0 Buffers for Clustered VLIW Processors.
Proceedings of the 36th Annual International Symposium on Microarchitecture, 2003

Local Scheduling Techniques for Memory Coherence in a Clustered VLIW Processor with a Distributed Data Cache.
Proceedings of the 1st IEEE / ACM International Symposium on Code Generation and Optimization (CGO 2003), 2003

2002
Effective instruction scheduling techniques for an interleaved cache clustered VLIW processor.
Proceedings of the 35th Annual International Symposium on Microarchitecture, 2002

An interleaved cache clustered VLIW processor.
Proceedings of the 16th international conference on Supercomputing, 2002


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