According to our database1, Enric Gibert authored at least 20 papers between 2002 and 2017.
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HW/SW co-designed processors: Challenges, design choices and a simulation infrastructure for evaluation.
Proceedings of the 2017 IEEE International Symposium on Performance Analysis of Systems and Software, 2017
Development and validation of hydrophobic molecular fields derived from the quantum mechanical IEF/PCM-MST solvation models in 3D-QSAR.
Journal of Computational Chemistry, 2016
Quantitative characterization of the software layer of a HW/SW co-designed processor.
Proceedings of the 2016 IEEE International Symposium on Workload Characterization, 2016
Profiling Support for Runtime Managed Code: Next Generation Performance Monitoring Units.
Computer Architecture Letters, 2015
Warm-Up Simulation Methodology for HW/SW Co-Designed Processors.
Proceedings of the 12th Annual IEEE/ACM International Symposium on Code Generation and Optimization, 2014
Accurate off-line phase classification for HW/SW co-designed processors.
Proceedings of the Computing Frontiers Conference, CF'14, 2014
Speculative hardware/software co-designed floating-point multiply-add fusion.
Proceedings of the Architectural Support for Programming Languages and Operating Systems, 2014
Performance analysis and predictability of the software layer in dynamic binary translators/optimizers.
Proceedings of the Computing Frontiers Conference, 2013
DDGacc: boosting dynamic DDG-based binary optimizations through specialized hardware support.
Proceedings of the 8th International Conference on Virtual Execution Environments, 2012
Global productiveness propagation: a code optimization technique to speculatively prune useless narrow computations.
Proceedings of the ACM SIGPLAN/SIGBED 2011 conference on Languages, 2011
Boosting single-thread performance in multi-core systems through fine-grain multi-threading.
Proceedings of the 36th International Symposium on Computer Architecture (ISCA 2009), 2009
Anaphase: A Fine-Grain Thread Decomposition Scheme for Speculative Multithreading.
Proceedings of the PACT 2009, 2009
A dynamically reconfigurable cache for multithreaded processors.
J. Embedded Computing, 2006
Instruction scheduling for a clustered VLIW processor with a word-interleaved cache.
Concurrency and Computation: Practice and Experience, 2006
Distributed Data Cache Designs for Clustered VLIW Processors.
IEEE Trans. Computers, 2005
Variable-Based Multi-module Data Caches for Clustered VLIW Processors.
Proceedings of the 14th International Conference on Parallel Architectures and Compilation Techniques (PACT 2005), 2005
Flexible Compiler-Managed L0 Buffers for Clustered VLIW Processors.
Proceedings of the 36th Annual International Symposium on Microarchitecture, 2003
Local Scheduling Techniques for Memory Coherence in a Clustered VLIW Processor with a Distributed Data Cache.
Proceedings of the 1st IEEE / ACM International Symposium on Code Generation and Optimization (CGO 2003), 2003
Effective instruction scheduling techniques for an interleaved cache clustered VLIW processor.
Proceedings of the 35th Annual International Symposium on Microarchitecture, 2002
An interleaved cache clustered VLIW processor.
Proceedings of the 16th international conference on Supercomputing, 2002