Francesco Brandonisio

According to our database1, Francesco Brandonisio authored at least 9 papers between 2010 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2023
On the Design Challenges of Class-C Oscillators in Ultra-Scaled CMOS Technologies.
Proceedings of the 18th Conference on Ph.D Research in Microelectronics and Electronics, 2023

2021
Analytical Modeling of Jitter in Bang-Bang CDR Circuits Featuring Phase Interpolation.
IEEE Trans. Very Large Scale Integr. Syst., 2021

2018
Design of a half-rate receiver for a 10Gbps automotive serial interface with 1-tap-unrolled 4-taps DFE and custom CDR algorithm.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

2016
Design of a transmitter for high-speed serial interfaces in automotive micro-controller.
Proceedings of the 39th International Convention on Information and Communication Technology, 2016

Design of a 8-taps, 10Gbps transmitter for automotive micro-controllers.
Proceedings of the 2016 IEEE Asia Pacific Conference on Circuits and Systems, 2016

2013
Implementation of a pulse-holding Time-to-Digital Converter on an FPGA.
Proceedings of the 21st European Conference on Circuit Theory and Design, 2013

2011
First order noise shaping in all digital PLLs.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

2010
An all-digital PLL with a first order noise shaping Time-to-Digital Converter.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

First Order Noise Shaping Local-Oscillator Based Time-to-Digital Converter.
Proceedings of the 17th IEEE International Conference on Electronics, 2010


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