Pierpaolo Palestri
According to our database1,
Pierpaolo Palestri
authored at least 30 papers
between 2004 and 2021.
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Bibliography
2021
Sensitivity, Noise and Resolution in a BEOL-Modified Foundry-Made ISFET with Miniaturized Reference Electrode for Wearable Point-of-Care Applications.
Sensors, 2021
2020
Design and Simulation of a 12 Gb/s Transceiver With 8-Tap FFE, Offset-Compensated Samplers and Fully Adaptive 1-Tap Speculative/3-Tap DFE and Sampling Phase for MIPI A-PHY Applications.
IEEE Trans. Circuits Syst. II Express Briefs, 2020
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020
2019
A simple and fast tool for the modelling of inter-symbol interference and equalization in high-speed chip-to-chip interfaces.
Proceedings of the 42nd International Convention on Information and Communication Technology, 2019
Automotive-Range Characterization of a 11 Gb/s Transceiver for Automotive Microcontroller Applications with 8-Tap FFE, 1-Tap Unrolled/3-Tap DFE and Offset-Compensated Samplers.
Proceedings of the 2019 IEEE Asia Pacific Conference on Circuits and Systems, 2019
2018
Design and Characterization of a 9.2-Gb/s Transceiver for Automotive Microcontroller Applications With 8-Taps FFE and 1-Tap Unrolled/4-Taps DFE.
IEEE Trans. Circuits Syst. II Express Briefs, 2018
Sub-mW multi-Gbps chip-to-chip communication Links for Ultra-Low Power IoT end-nodes.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
Design of a half-rate receiver for a 10Gbps automotive serial interface with 1-tap-unrolled 4-taps DFE and custom CDR algorithm.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
2017
Experimental characterization of the static noise margins of strained silicon complementary tunnel-FET SRAM.
Proceedings of the 47th European Solid-State Device Research Conference, 2017
2016
Design of a transmitter for high-speed serial interfaces in automotive micro-controller.
Proceedings of the 39th International Convention on Information and Communication Technology, 2016
Performance study of strained III-V materials for ultra-thin body transistor applications.
Proceedings of the 46th European Solid-State Device Research Conference, 2016
Proceedings of the 46th European Solid-State Device Research Conference, 2016
Proceedings of the 2016 IEEE Asia Pacific Conference on Circuits and Systems, 2016
2015
Design and implementation of switched coil LC-VCOs in the GHz range using the self-inductance technique.
Int. J. Circuit Theory Appl., 2015
State-of-the-art semi-classical Monte Carlo method for carrier transport in nanoscale transistors.
Proceedings of the 38th International Convention on Information and Communication Technology, 2015
Proceedings of the 45th European Solid State Device Research Conference, 2015
2014
Proceedings of the 37th International Convention on Information and Communication Technology, 2014
Analysis of TFET based 6T SRAM cells implemented with state of the art silicon nanowires.
Proceedings of the 44th European Solid State Device Research Conference, 2014
Proceedings of the 44th European Solid State Device Research Conference, 2014
2013
Proceedings of the 5th IEEE International Workshop on Advances in Sensors and Interfaces, 2013
Proceedings of the European Solid-State Device Research Conference, 2013
2012
A Multi-Subband Monte Carlo study of electron transport in strained SiGe n-type FinFETs.
Proceedings of the 2012 European Solid-State Device Research Conference, 2012
2011
IEEE Trans. Circuits Syst. II Express Briefs, 2011
2010
A numerical model for the oscillation frequency, the amplitude and the phase-noise of MOS-current-mode-logic ring oscillators.
Int. J. Circuit Theory Appl., 2010
2009
Design of Ultra-Wideband Low-Noise Amplifiers in 45-nm CMOS Technology: Comparison Between Planar Bulk and SOI FinFET Devices.
IEEE Trans. Circuits Syst. I Regul. Pap., 2009
Proceedings of the 35th European Solid-State Circuits Conference, 2009
2008
IEEE Trans. Circuits Syst. I Regul. Pap., 2008
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008
2007
IEEE Trans. Circuits Syst. I Regul. Pap., 2007
2004
Modeling, design and characterization of a new low jitter analog dual tuning LC-VCO PLL architecture.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004