Gaetano Palumbo

IEEE Trans. Circuits Syst. I Regul. Pap., 2023

An Energy-Efficient Design Strategy for Dickson Charge Pumps with Linear Distributed Capacitance.

[BibT_eX]

[DOI]

Proceedings of the 21st IEEE Interregional NEWCAS Conference, 2023

Triple Clock Boosted Voltage Multiplier: A Design Strategy to Heavily Reduce Rise Time.

[BibT_eX]

[DOI]

Proceedings of the 21st IEEE Interregional NEWCAS Conference, 2023

Fully On-Chip Charge Pump-based Boost Converter in 65-nm CMOS for Single Solar Cell Powered IC.

[BibT_eX]

[DOI]

Carlos Aristoteles De la Cruz

Proceedings of the IEEE International Symposium on Circuits and Systems, 2023

GBW Optimization in Two-Stage OTAs Operating in Weak Inversion.

[BibT_eX]

[DOI]

Javier Beloso-Legarra

Antonio Lopez-Martin

Proceedings of the 38th Conference on Design of Circuits and Integrated Systems, 2023

2022

Two-Stage OTA With All Subthreshold MOSFETs and Optimum GBW to DC-Current Ratio.

[BibT_eX]

[DOI]

Javier Beloso-Legarra

IEEE Trans. Circuits Syst. II Express Briefs, 2022

A Bulk Current Regulation Technique for Dual-Branch Cross-Coupled Charge Pumps.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2022

The Dickson Charge Pump as a Signal Amplifier.

[BibT_eX]

[DOI]

Federico Nicolas Guerrero

IEEE Trans. Circuits Syst. I Regul. Pap., 2022

Single miller capacitor frequency compensation techniques: Theoretical comparison and critical review.

[BibT_eX]

[DOI]

Int. J. Circuit Theory Appl., 2022

Double-Differential Amplifier for sEMG Measurement by Means of a Current-Mode Approach.

[BibT_eX]

[DOI]

Enrique Mario Spinelli

IEEE Access, 2022

Analysis and Comparison in the Energy-Delay Space of Nanometer CMOS One-Bit Full-Adders.

[BibT_eX]

[DOI]

IEEE Access, 2022

A Novel Clock Gating Approach for the Design of Low-Power Linear Feedback Shift Registers.

[BibT_eX]

[DOI]

IEEE Access, 2022

A Charge Loss Aware Advanced Model of Dickson Voltage Multipliers.

[BibT_eX]

[DOI]

IEEE Access, 2022

A Methodology to Derive a Symbolic Transfer Function for Multistage Amplifiers.

[BibT_eX]

[DOI]

Hamed Aminzadeh

IEEE Access, 2022

2021

A Very-Low-Voltage Frequency Divider in Folded MOS Current Mode Logic With Complementary n- and p-type Flip-Flops.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2021

Charge Pumps for Ultra-Low-Power Applications: Analysis, Design, and New Solutions.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2021

Design of Three-Stage OTA Based on Settling-Time Requirements Including Large and Small Signal Behavior.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2021

Design of Low-Voltage Power Efficient Frequency Dividers in Folded MOS Current Mode Logic.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2021

Design of CMOS three-stage amplifiers for near-to-minimum settling-time.

[BibT_eX]

[DOI]

Microelectron. J., 2021

A Memory-Targeted Dynamic Reconfigurable Charge Pump to Achieve a Power Consumption Reduction in IoT Nodes.

[BibT_eX]

[DOI]

IEEE Access, 2021

Dickson Charge Pump: Design Strategy for Optimum Efficiency.

[BibT_eX]

[DOI]

Proceedings of the 19th IEEE International New Circuits and Systems Conference, 2021

Comparison of the Wide-Frequency Range Dynamic Behavior of the Dickson and Cockcroft-Walton Voltage Multipliers.

[BibT_eX]

[DOI]

Proceedings of the 64th IEEE International Midwest Symposium on Circuits and Systems, 2021

Design of Three-Stage OTAs from Settling-Time and Slew-Rate Constraints.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

A Low-Voltage High-Performance Frequency Divider exploiting Folded MCML.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

2020

A Novel 0.5 V MCML D-Flip-Flop Topology Exploiting Forward Body Bias Threshold Lowering.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2020

A Multi-Folded MCML for Ultra-Low-Voltage High-Performance in Deeply Scaled CMOS.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst., 2020

Charge Pump Improvement for Energy Harvesting Applications by Node Pre-Charging.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst., 2020

A High-Performance Charge Pump Topology for Very-Low-Voltage Applications.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2020

Delay models and design guidelines for MCML gates with resistor or PMOS load.

[BibT_eX]

[DOI]

Microelectron. J., 2020

Linear distribution of capacitance in Dickson charge pumps to reduce rise time.

[BibT_eX]

[DOI]

Int. J. Circuit Theory Appl., 2020

Current-mode body-biased switch to increase performance of linear charge pumps.

[BibT_eX]

[DOI]

Int. J. Circuit Theory Appl., 2020

A simple and effective design strategy to increase power conversion efficiency of linear charge pumps.

[BibT_eX]

[DOI]

Int. J. Circuit Theory Appl., 2020

A Subthreshold Cross-Coupled Hybrid Charge Pump for 50-mV Cold-Start.

[BibT_eX]

[DOI]

IEEE Access, 2020

2019

In-Depth Analysis of Pole-Zero Compensations in CMOS Operational Transconductance Amplifiers.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2019

Optimized Charge Pump With Clock Booster for Reduced Rise Time or Silicon Area.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2019

Class-AB CMOS output stages suitable for low-voltage amplifiers in nanometer technologies.

[BibT_eX]

[DOI]

Microelectron. J., 2019

2018

Dual Push-Pull High-Speed Rail-to-Rail CMOS Buffer Amplifier for Flat-Panel Displays.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2018

Switched-Capacitor Power Management Integrated Circuit for Autonomous Internet of Things Node.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2018

High-Performance Three-Stage Single-Miller CMOS OTA With No Upper Limit of CL.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2018

Guest Editorial Special Issue on Selected Papers from PRIME 2017 and SMACD 2017.

[BibT_eX]

[DOI]

Giulia Di Capua

Nuno Horta

Francisco V. Fernández

Integr., 2018

Bessel-like compensation of three-stage operational transconductance amplifiers.

[BibT_eX]

[DOI]

Int. J. Circuit Theory Appl., 2018

A Novel Very Low Voltage Topology to implement MCML XOR Gates.

[BibT_eX]

[DOI]

Davide Bellizia

Proceedings of the 14th Conference on Ph.D. Research in Microelectronics and Electronics, 2018

Settling-time oriented OTA design through the approximation of the ideal delay.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

Non-Inverting Class-AB CMOS Output Stage for Driving High-Capacitive Loads.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

Three-stage single-miller CMOS OTA driving 10 nF with 1.46-MHz GBW.

[BibT_eX]

[DOI]

Proceedings of the 2018 International Conference on IC Design & Technology, 2018

A Novel 0.6V MCML D-Latch Topology exploiting Dynamic Body Bias Threshold Lowering.

[BibT_eX]

[DOI]

Proceedings of the 25th IEEE International Conference on Electronics, Circuits and Systems, 2018

Design of CMOS OTAs with Settling-Time Constraints.

[BibT_eX]

[DOI]

Proceedings of the 25th IEEE International Conference on Electronics, Circuits and Systems, 2018

A Clock Boosted Charge Pump with Reduced Rise Time.

[BibT_eX]

[DOI]

Proceedings of the 25th IEEE International Conference on Electronics, Circuits and Systems, 2018

2017

Design of Low-Voltage High-Speed CML D-Latches in Nanometer CMOS Technologies.

[BibT_eX]

[DOI]

Davide Bellizia

IEEE Trans. Very Large Scale Integr. Syst., 2017

The noise performance of CMOS Miller operational transconductance amplifiers with embedded current-buffer frequency compensation.

[BibT_eX]

[DOI]

Int. J. Circuit Theory Appl., 2017

Robust design of CMOS amplifiers oriented to settling-time specification.

[BibT_eX]

[DOI]

Int. J. Circuit Theory Appl., 2017

2016

Optimized Active Single-Miller Capacitor Compensation With Inner Half-Feedforward Stage for Very High-Load Three-Stage OTAs.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2016

Verilog-a modeling of Silicon Photo-Multipliers.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

A 0.003-mm2 50-mW three-stage amplifier driving 10-nF with 2.7-MHz GBW.

[BibT_eX]

[DOI]

Proceedings of the 2016 IEEE International Conference on Electronics, Circuits and Systems, 2016

2015

Integrated Quenching-and-Reset Circuit for Single-Photon Avalanche Diodes.

[BibT_eX]

[DOI]

IEEE Trans. Instrum. Meas., 2015

High-Performance Four-Stage CMOS OTA Suitable for Large Capacitive Loads.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2015

Design Methodology of Subthreshold Three-Stage CMOS OTAs Suitable for Ultra-Low-Power Low-Area and High Driving Capability.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2015

Three-Stage Dynamic-Biased CMOS Amplifier With a Robust Optimization of the Settling Time.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2015

Variations in Nanometer CMOS Flip-Flops: Part I - Impact of Process Variations on Timing.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2015

Variations in Nanometer CMOS Flip-Flops: Part II - Energy Variability and Impact of Other Sources of Variations.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2015

A new enhanced PSPICE implementation of the equivalent circuit model of SiPM detectors.

[BibT_eX]

[DOI]

Proceedings of the IEEE 13th International New Circuits and Systems Conference, 2015

Variability budgetin pulsed flip-flops.

[BibT_eX]

[DOI]

Proceedings of the IEEE 13th International New Circuits and Systems Conference, 2015

195-nW 120-dB subthreshold CMOS OTA driving up to 200 pF and occupying only 4.4-10-3 mm2.

[BibT_eX]

[DOI]

Proceedings of the 2015 IEEE International Conference on Electronics, 2015

Comparative analysis of the robustness of master-slave flip-flops against variations.

[BibT_eX]

[DOI]

Proceedings of the 2015 IEEE International Conference on Electronics, 2015

Single-miller all-passive compensation network for three-stage OTAs.

[BibT_eX]

[DOI]

Proceedings of the European Conference on Circuit Theory and Design, 2015

PVT variations in differential flip-flops: A comparative analysis.

[BibT_eX]

[DOI]

Proceedings of the European Conference on Circuit Theory and Design, 2015

2014

Novel Class of Energy-Efficient Very High-Speed Conditional Push-Pull Pulsed Latches.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2014

Self-Biased Dual-Path Push-Pull Output Buffer Amplifier for LCD Column Drivers.

[BibT_eX]

[DOI]

Fermin Esparza-Alfaro

IEEE Trans. Circuits Syst. I Regul. Pap., 2014

Low-Power Class-AB CMOS Voltage Feedback Current Operational Amplifier With Tunable Gain and Bandwidth.

[BibT_eX]

[DOI]

Fermin Esparza-Alfaro

IEEE Trans. Circuits Syst. II Express Briefs, 2014

A new accurate analytical expression for the SiPM transient response to single photons.

[BibT_eX]

[DOI]

Proceedings of the 21st IEEE International Conference on Electronics, Circuits and Systems, 2014

High-performance frequency compensation topology for four-stage OTAs.

[BibT_eX]

[DOI]

Proceedings of the 21st IEEE International Conference on Electronics, Circuits and Systems, 2014

Monolithic quenching-and-reset circuit for single-photon avalanche diodes.

[BibT_eX]

[DOI]

Proceedings of the 21st IEEE International Conference on Electronics, Circuits and Systems, 2014

CMOS class-AB tunable voltage-feedback current operational amplifier.

[BibT_eX]

[DOI]

Fermin Esparza-Alfaro

Salvatore Permisi

Proceedings of the 21st IEEE International Conference on Electronics, Circuits and Systems, 2014

2013

Optimized frequency compensation topology for low-power three-stage OTAs.

[BibT_eX]

[DOI]

Proceedings of the 21st European Conference on Circuit Theory and Design, 2013

A simple extraction procedure for determining the electrical parameters in Silicon Photomultipliers.

[BibT_eX]

[DOI]

Proceedings of the 21st European Conference on Circuit Theory and Design, 2013

2012

Reconsidering High-Speed Design Criteria for Transmission-Gate-Based Master-Slave Flip-Flops.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2012

A Simple Circuit Approach to Reduce Delay Variations in Domino Logic Gates.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2012

Robust Miller Compensation With Current Amplifiers Applied to LDO Voltage Regulators.

[BibT_eX]

[DOI]

Ester Spitale

IEEE Trans. Circuits Syst. I Regul. Pap., 2012

An Accurate Ultra-Compact I-V Model for Nanometer MOS Transistors With Applications on Digital Circuits.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2012

Behavioral modeling of statistical phenomena of single-photon avalanche diodes.

[BibT_eX]

[DOI]

Int. J. Circuit Theory Appl., 2012

From energy-delay metrics to constraints on the design of digital circuits.

[BibT_eX]

[DOI]

Int. J. Circuit Theory Appl., 2012

Conditional push-pull pulsed latches with 726fJ·ps energy-delay product in 65nm CMOS.

[BibT_eX]

[DOI]

Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012

Logic gates dynamic modeling by means of an ultra-compact MOS model.

[BibT_eX]

[DOI]

Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

A simple keeper topology to reduce delay variations in nanometer domino logic.

[BibT_eX]

[DOI]

Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

2011

Analysis and Comparison in the Energy-Delay-Area Domain of Nanometer CMOS Flip-Flops: Part II - Results and Figures of Merit.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2011

Analysis and Comparison in the Energy-Delay-Area Domain of Nanometer CMOS Flip-Flops: Part I - Methodology and Design Strategies.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2011

Optimized design of parallel carry-select adders.

[BibT_eX]

[DOI]

Integr., 2011

Self-biased dual-path push-pull output buffer amplifier topology for LCD driver applications.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

Verilog-A modeling of SPAD statistical phenomena.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

TG Master-Slave FFs: High-speed optimization.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

DET FF topologies: A detailed investigation in the energy-delay-area domain.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

Figures of merit for class AB input stages.

[BibT_eX]

[DOI]

Ramón González Carvajal

Proceedings of the 20th European Conference on Circuit Theory and Design, 2011

An ultra-compact MOS model in nanometer technologies.

[BibT_eX]

[DOI]

Proceedings of the 20th European Conference on Circuit Theory and Design, 2011

Inverter transfer curves and SRAM noise margin evaluation based on an ultra-compact MOS model.

[BibT_eX]

[DOI]

Proceedings of the 20th European Conference on Circuit Theory and Design, 2011

2010

Understanding the Effect of Process Variations on the Delay of Static and Domino Logic.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2010

General Strategies to Design Nanometer Flip-Flops in the Energy-Delay Space.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2010

Flip-Flop Energy/Performance Versus Clock Slope and Impact on the Clock Network Design.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2010

Improved Low-Power High-Speed Buffer amplifier with slew-Rate Enhancement for LCD Applications.

[BibT_eX]

[DOI]

J. Circuits Syst. Comput., 2010

Analytical comparison of reversed nested Miller frequency compensation techniques.

[BibT_eX]

[DOI]

Int. J. Circuit Theory Appl., 2010

Simple and accurate modeling of the output transition time in nanometer CMOS gates.

[BibT_eX]

[DOI]

Int. J. Circuit Theory Appl., 2010

Step-response optimisation techniques for low-power, high-load, three-stage operational amplifiers driving large capacitive loads.

[BibT_eX]

[DOI]

IET Circuits Devices Syst., 2010

Physical Design Aware Comparison of Flip-Flops for High-Speed Energy-Efficient VLSI Circuits.

[BibT_eX]

[DOI]

Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation, 2010

Low-power dual-active class-AB buffer amplifier with self-biasing network for LCD column drivers.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

A novel low-power high-speed rail-to-rail class-B buffer amplifier for LCD output drivers.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

Analytical figure of merit evaluation of RNMC networks for low-power three-stage OTAs.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

Clock distribution in clock domains with Dual-Edge-Triggered Flip-Flops to improve energy-efficiency.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

2009

Analysis and Modeling of Energy Consumption in RLC Tree Circuits.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2009

Improved Power-Efficient RNMC Technique with voltage Buffer and Nulling resistors for Low-Power High-Load Three-Stage amplifiers.

[BibT_eX]

[DOI]

J. Circuits Syst. Comput., 2009

Propagation delay of an RC-circuit with a ramp input: An analytical very accurate and simple model.

[BibT_eX]

[DOI]

Int. J. Circuit Theory Appl., 2009

Approach to analyse and design nearly sinusoidal oscillators.

[BibT_eX]

[DOI]

IET Circuits Devices Syst., 2009

A New Advanced RNMC Technique with Dual-active Current and Voltage Buffers for Low-power High-load Three-stage Amplifiers.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

Step-response Optimization Techniques for Low-power Three-stage Operational Amplifiers for Large Capacitive Load Applications.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

Metrics and Design Considerations on the Energy-delay Tradeoff of Digital Circuits.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

Exploitation of the phasor approach for closed-form solution of the Van der Pol's oscillator and sinusoidal oscillators with high-order nonlinearity.

[BibT_eX]

[DOI]

Proceedings of the 16th IEEE International Conference on Electronics, 2009

A high-speed low-power output buffer amplifier for large-size LCD applications.

[BibT_eX]

[DOI]

Proceedings of the 16th IEEE International Conference on Electronics, 2009

An efficient RNM compensation topology with voltage buffer and nulling resistors for large-capacitive-load three-stage OTAs.

[BibT_eX]

[DOI]

Proceedings of the 16th IEEE International Conference on Electronics, 2009

Analysis of the impact of random process variations in CMOS tapered buffers.

[BibT_eX]

[DOI]

Proceedings of the 16th IEEE International Conference on Electronics, 2009

Optimum clock slope for flip-flops within a clock domain: Analysis and a case study.

[BibT_eX]

[DOI]

Proceedings of the 16th IEEE International Conference on Electronics, 2009

Correct procedures to evaluate the effect of intradie variations on the delay variability of digital circuits.

[BibT_eX]

[DOI]

Proceedings of the 19th European Conference on Circuit Theory and Design, 2009

Impact of clock slope on energy/delay of pulsed flip-flops and optimum clock domain design.

[BibT_eX]

[DOI]

Proceedings of the 19th European Conference on Circuit Theory and Design, 2009

2008

High-Speed and Compact Quenching Circuit for Single-Photon Avalanche Diodes.

[BibT_eX]

[DOI]

IEEE Trans. Instrum. Meas., 2008

Miller Theorem for Weakly Nonlinear Feedback Circuits and Application to CE Amplifier.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2008

Wien-Type Oscillators: Evaluation and Optimization of Harmonic Distortion.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2008

Comparison of the Frequency Compensation Techniques for CMOS Two-Stage Miller OTAs.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2008

Power-Aware Design of Nanometer MCML Tapered Buffers.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2008

AMOLED pixel driver circuits based on poly-Si TFTs: A comparison.

[BibT_eX]

[DOI]

Integr., 2008

Analytical comparison of frequency compensation techniques in three-stage amplifiers.

[BibT_eX]

[DOI]

Int. J. Circuit Theory Appl., 2008

An approach to model high-frequency distortion in negative-feedback amplifiers.

[BibT_eX]

[DOI]

Int. J. Circuit Theory Appl., 2008

Single Miller capacitor frequency compensation with nulling resistor for three-stage amplifiers.

[BibT_eX]

[DOI]

Int. J. Circuit Theory Appl., 2008

Accurate model for single-photon avalanche diodes.

[BibT_eX]

[DOI]

Pier Giorgio Fallica

IET Circuits Devices Syst., 2008

Design methodology of Miller frequency compensation with current buffer/amplifier.

[BibT_eX]

[DOI]

IET Circuits Devices Syst., 2008

Understanding the Effect of Intradie Random Process Variations in Nanometer Domino Logic.

[BibT_eX]

[DOI]

Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2008

Low-voltage LDO Compensation Strategy based on Current Amplifiers.

[BibT_eX]

[DOI]

Ester Spitale

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

Explicit energy evaluation in RLC tree circuits with ramp inputs.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

Power-delay optimization in MCML tapered buffers.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

Design guidelines for minimum harmonic distortion in a wien oscillator with automatic amplitude control system.

[BibT_eX]

[DOI]

Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, 2008

Design guidelines for high-speed Transmission-gate latches: Analysis and comparison.

[BibT_eX]

[DOI]

Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, 2008

Energy evaluation in RLC tree circuits with exponential input.

[BibT_eX]

[DOI]

Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, 2008

Analysis of the impact of process variations on static logic circuits versus fan-in.

[BibT_eX]

[DOI]

Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, 2008

2007

Propagation Delay of an RC-Chain With a Ramp Input.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2007

Advances in Reversed Nested Miller Compensation.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2007

Improved Reversed Nested Miller Frequency Compensation Technique With Voltage Buffer and Resistor.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2007

Resistance of Feedback Amplifiers: A Novel Representation.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2007

Design Procedures for Three-Stage CMOS OTAs With Nested-Miller Compensation.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2007

Interconnect-Aware Design of Fast Large Fan-In CMOS Multiplexers.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2007

Mixed Full Adder topologies for high-performance low-power arithmetic circuits.

[BibT_eX]

[DOI]

Microelectron. J., 2007

Rosenstark-like Representation of Feedback Amplifier Resistance.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

Miller Compensation: Optimization with Current Buffer/Amplifier.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

Delay Variability Due to Supply Variations in Transmission-Gate Full Adders.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

Design of Fast Large Fan-In CMOS Multiplexers Accounting for Interconnects.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

High-Speed/Low-Power Mixed Full Adder Chains: Analysis and Comparison versus Technology.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

Efficient and Accurate Models of Output Transition Time in CMOS Logic.

[BibT_eX]

[DOI]

Proceedings of the 14th IEEE International Conference on Electronics, 2007

Distortion analysis in the frequency domain of a Gm-C biquad.

[BibT_eX]

[DOI]

Proceedings of the 18th European Conference on Circuit Theory and Design, 2007

Highly-accurate propagation delay analytical model of an RC-circuit with a ramp input.

[BibT_eX]

[DOI]

Proceedings of the 18th European Conference on Circuit Theory and Design, 2007

LDO compensation strategy based on current buffer/amplifiers.

[BibT_eX]

[DOI]

Ester Spitale

Proceedings of the 18th European Conference on Circuit Theory and Design, 2007

A generalization of Miller formulae for nonlinear feedback networks.

[BibT_eX]

[DOI]

Proceedings of the 18th European Conference on Circuit Theory and Design, 2007

Energy consumption in RLC tree circuits.

[BibT_eX]

[DOI]

Proceedings of the 18th European Conference on Circuit Theory and Design, 2007

Very high-speed carry computation based on mixed dynamic/transmission-gate Full Adders.

[BibT_eX]

[DOI]

Proceedings of the 18th European Conference on Circuit Theory and Design, 2007

2006

Energy Consumption in RC Tree Circuits.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2006

Impact of Supply Voltage Variations on Full Adder Delay: Analysis and Comparison.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2006

Charge pump circuits with only capacitive loads: optimized design.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2006

Three-Stage CMOS OTA for Large Capacitive Loads With Efficient Frequency Compensation Scheme.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2006

Distortion analysis of Miller-compensated three-stage amplifiers.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2006

Effects of nonlinear feedback in the frequency domain.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2006

Design strategies of cascaded CML gates.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2006

Design of High-Speed Power-Efficient MOS Current-Mode Logic Frequency Dividers.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2006

A fast driver circuit for single-photon sensors.

[BibT_eX]

[DOI]

Pier Giorgio Fallica

Microelectron. J., 2006

Analysis and evaluation of harmonic distortion in the tunnel diode oscillator.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

Active reversed nested Miller compensation for three-stage amplifiers.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

Efficient output transition time modeling in CMOS gates with ramp/exponential inputs.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

Nanometer MCML gates: models and design considerations.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

Delay uncertainty due to supply variations in static and dynamic full adders.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

Analysis of Harmonic Distortion in the Colpitts Oscillator.

[BibT_eX]

[DOI]

Proceedings of the 13th IEEE International Conference on Electronics, 2006

NMOS Low Drop-Out Regulator with Dynamic Biasing.

[BibT_eX]

[DOI]

Proceedings of the 13th IEEE International Conference on Electronics, 2006

Modeling of Feedback Analog Circuits with VHDL.

[BibT_eX]

[DOI]

Proceedings of the 13th IEEE International Conference on Electronics, 2006

RC-Chain: a Simple Model of Delay with a Ramp Input.

[BibT_eX]

[DOI]

Proceedings of the 13th IEEE International Conference on Electronics, 2006

Modeling of Delay Variability Due to Supply Variations in Pass-Transistor and Static Full Adders.

[BibT_eX]

[DOI]

Proceedings of the 13th IEEE International Conference on Electronics, 2006

A Design Methodology for High-Speed Low-Power MCML Frequency Dividers.

[BibT_eX]

[DOI]

Proceedings of the 13th IEEE International Conference on Electronics, 2006

2005

Low-voltage high-drive CMOS current feedback op-amp.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2005

Nonidealities of Tow-Thomas biquads Using VOA- and CFOA-based Miller integrators.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2005

Design and Comparison of Very Low-Voltage CMOS Output Stages.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2005

A high-performance very low-voltage current sense amplifier for nonvolatile memories.

[BibT_eX]

[DOI]

Antonino Conte

Gianbattista Lo Giudice

Alfredo Signorello

IEEE J. Solid State Circuits, 2005

Efficiency model of boost dc-dc PWM converters.

[BibT_eX]

[DOI]

Int. J. Circuit Theory Appl., 2005

Modelling and design considerations on CML gates under high-current effects.

[BibT_eX]

[DOI]

Int. J. Circuit Theory Appl., 2005

Power-delay optimization of D-latch/MUX source coupled logic gates.

[BibT_eX]

[DOI]

Int. J. Circuit Theory Appl., 2005

Energy Consumption in RC Tree Circuits with Exponential Inputs: An Analytical Model.

[BibT_eX]

[DOI]

Proceedings of the Integrated Circuit and System Design, 2005

Optimized design of source coupled logic gates in GaAs HEMT technology.

[BibT_eX]

[DOI]

Pasquale Tommasino

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Well-defined design procedure for a three-stage CMOS OTA.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Design techniques for low-power cascaded CML gates.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Design strategy to minimize rise time and silicon area of charge pump with only capacitive loads.

[BibT_eX]

[DOI]

Luigi Innacolo

Proceedings of the 12th IEEE International Conference on Electronics, 2005

A comparison between amoled poly-TFT driver circuits.

[BibT_eX]

[DOI]

Proceedings of the 12th IEEE International Conference on Electronics, 2005

Behavioral model of charge pumps with VHDL.

[BibT_eX]

[DOI]

Proceedings of the 12th IEEE International Conference on Electronics, 2005

VHDL-based modeling of a DC-DC boost converter.

[BibT_eX]

[DOI]

Proceedings of the 12th IEEE International Conference on Electronics, 2005

A novel model for single photon detectors.

[BibT_eX]

[DOI]

Proceedings of the 12th IEEE International Conference on Electronics, 2005

Comparison of methods for predicting distortion in class-AB stages.

[BibT_eX]

[DOI]

Proceedings of the 12th IEEE International Conference on Electronics, 2005

Analysis and optimization of a low-voltage class-AB output stage.

[BibT_eX]

[DOI]

Proceedings of the 12th IEEE International Conference on Electronics, 2005

A fast active quenching and recharging circuit for single-photon avalanche diodes.

[BibT_eX]

[DOI]

Giorgio Fallica

Proceedings of the 2005 European Conference on Circuit Theory and Design, 2005

Optimized design of ECL gates with a power constraint.

[BibT_eX]

[DOI]

Proceedings of the 2005 European Conference on Circuit Theory and Design, 2005

Statistical analysis of CMOS current reference.

[BibT_eX]

[DOI]

Maurizio Gaibotti

Michelangelo Pisasale

Proceedings of the 2005 European Conference on Circuit Theory and Design, 2005

New analytical approach to evaluate harmonic distortion in nonlinear feedback amplifiers.

[BibT_eX]

[DOI]

Proceedings of the 2005 European Conference on Circuit Theory and Design, 2005

Distortion analysis of three-stage amplifiers with reversed nested-Miller compensation.

[BibT_eX]

[DOI]

Proceedings of the 2005 European Conference on Circuit Theory and Design, 2005

Guidelines for designing class-AB output stages.

[BibT_eX]

[DOI]

Proceedings of the 2005 European Conference on Circuit Theory and Design, 2005

2004

Evaluation of energy consumption in RC ladder circuits driven by a ramp input.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2004

Effect of CFOA nonidealities in Miller integrator cells.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2004

Exploiting the high-frequency performance of low-voltage low-power SC filters.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2004

Harmonic distortion in three-stage nested-Miller-compensated amplifiers.

[BibT_eX]

[DOI]

Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

Sigma-Delta A/D fuzzy converter.

[BibT_eX]

Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

Low-voltage linear voltage regulator suitable for memories.

[BibT_eX]

[DOI]

Stello Matteo Billé

Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

A gate-level strategy to design Carry Select Adders.

[BibT_eX]

Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

A 1.35-V sense amplifier for non volatile memories based on current mode approach.

[BibT_eX]

[DOI]

Antonino Conte

Gianbattista Lo Giudice

Alfredo Signorello

Proceedings of the 33rd European Solid-State Circuits Conference, 2004

2003

Design guidelines for reversed nested Miller compensation in three-stage amplifiers.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2003

1.5-V CMOS CCII+ with high current-driving capability.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2003

A low-voltage low-power voltage reference based on subthreshold MOSFETs.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2003

Performance evaluation of the low-voltage CML D-latch topology.

[BibT_eX]

[DOI]

Integr., 2003

Analysis, modelling and optimization of a gain boosted telescopic amplifier.

[BibT_eX]

[DOI]

Int. J. Circuit Theory Appl., 2003

Performance comparison of Tow-Thomas biquad filters based on VOAs and CFOAs.

[BibT_eX]

[DOI]

Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

A new method for evaluating harmonic distortion in push-pull output stages.

[BibT_eX]

[DOI]

Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

A novel 1-V class-AB transconductor for improving speed performance in SC applications.

[BibT_eX]

[DOI]

Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

Design of low-voltage low-power SC filters for high-frequency applications.

[BibT_eX]

[DOI]

Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

A 1-V CMOS output stage with high linearity.

[BibT_eX]

[DOI]

Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

Design of MUX, XOR and D-latch SCL gates.

[BibT_eX]

[DOI]

Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

2002

Analysis and comparison on full adder block in submicron technology.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2002

Current-mode A/D fuzzy converter.

[BibT_eX]

[DOI]

IEEE Trans. Fuzzy Syst., 2002

Modelling of source-coupled logic gates.

[BibT_eX]

[DOI]

Int. J. Circuit Theory Appl., 2002

Modeling of Propagation Delay of a First Order Circuit with a Ramp Input.

[BibT_eX]

[DOI]

Proceedings of the Integrated Circuit Design. Power and Timing Modeling, 2002

An Approach to Energy Consumption Modeling in RC Ladder Circuits.

[BibT_eX]

[DOI]

Proceedings of the Integrated Circuit Design. Power and Timing Modeling, 2002

Modeling Propagation Delay of MUX, XOR, and D-Latch Source-Coupled Logic Gates.

[BibT_eX]

[DOI]

Proceedings of the Integrated Circuit Design. Power and Timing Modeling, 2002

Evaluation on power reduction applying gated clock approaches.

[BibT_eX]

[DOI]

Francesco Pappalardo

S. Sannella

Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

Analysis of power supply noise attenuation in a PTAT current source.

[BibT_eX]

[DOI]

Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

Analysis and optimization of gain-boosted telescopic amplifiers.

[BibT_eX]

[DOI]

Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

Power-delay trade-offs in SCL gates.

[BibT_eX]

[DOI]

Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

Voltage regulator based on an high-efficiency adaptive charge pump.

[BibT_eX]

[DOI]

Maurizio Gaibotti

Proceedings of the 2002 9th IEEE International Conference on Electronics, 2002

Propagation delay model of current driven RC chain.

[BibT_eX]

[DOI]

Proceedings of the 2002 9th IEEE International Conference on Electronics, 2002

A novel pseudo random bit generator for cryptography applications.

[BibT_eX]

[DOI]

Proceedings of the 2002 9th IEEE International Conference on Electronics, 2002

Comparison between Miller integrator cells using VOAs and CFOAs.

[BibT_eX]

[DOI]

Proceedings of the 2002 9th IEEE International Conference on Electronics, 2002

Hybrid nested Miller compensation with nulling resistors.

[BibT_eX]

[DOI]

Proceedings of the 2002 9th IEEE International Conference on Electronics, 2002

Statistical analysis of the resolution in a current-mode ADC.

[BibT_eX]

[DOI]

Proceedings of the 2002 9th IEEE International Conference on Electronics, 2002

A high-performance buffer for non-volatile memories.

[BibT_eX]

[DOI]

Proceedings of the 2002 9th IEEE International Conference on Electronics, 2002

Analysis and comparison of low-voltage CML D-latch.

[BibT_eX]

[DOI]

Proceedings of the 2002 9th IEEE International Conference on Electronics, 2002

Design guidelines for bipolar frequency dividers.

[BibT_eX]

[DOI]

Proceedings of the 2002 9th IEEE International Conference on Electronics, 2002

Low Power Strategy for a TFT Controller.

[BibT_eX]

[DOI]

Proceedings of the 2002 Euromicro Symposium on Digital Systems Design (DSD 2002), 2002

2001

Power estimation in adiabatic circuits: a simple and accurate model.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2001

A high‐performance CMOS CCII.

[BibT_eX]

[DOI]

Int. J. Circuit Theory Appl., 2001

Analysis and optimization of a novel CMOS multiplier.

[BibT_eX]

[DOI]

Int. J. Circuit Theory Appl., 2001

Modeling and minimization of power consumption in charge pump circuits.

[BibT_eX]

[DOI]

Maurizio Gaibotti

Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

Reversed nested Miller compensation with current follower.

[BibT_eX]

[DOI]

Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

Detailed frequency analysis of power supply rejection in Brokaw bandgap.

[BibT_eX]

[DOI]

Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

CML ring oscillators: oscillation frequency.

[BibT_eX]

[DOI]

Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

Built-In Self Test for Low Cost Testing of a 60 MHz Synchronous Flash Memory.

[BibT_eX]

[DOI]

Proceedings of the 7th IEEE International On-Line Testing Workshop (IOLTW 2001), 2001

Feedback amplifiers: a simplified analysis of harmonic distortion in the frequency domain.

[BibT_eX]

[DOI]

Proceedings of the 2001 8th IEEE International Conference on Electronics, 2001

A fuzzy controller for step-up DC/DC converters.

[BibT_eX]

[DOI]

Proceedings of the 2001 8th IEEE International Conference on Electronics, 2001

Delay estimation of SCL gates with output buffer.

[BibT_eX]

[DOI]

Proceedings of the 2001 8th IEEE International Conference on Electronics, 2001

Optimized design of high fan-in multiplexers using switches with driving capability.

[BibT_eX]

[DOI]

Proceedings of the 2001 8th IEEE International Conference on Electronics, 2001

2000

CMRR frequency response of CMOS operational transconductance amplifiers.

[BibT_eX]

[DOI]

IEEE Trans. Instrum. Meas., 2000

Modeling of Power Consumption of Adiabatic Gates versus Fan in and Comparison with Conventional Gates.

[BibT_eX]

[DOI]

Proceedings of the Integrated Circuit Design, 2000

A fuzzy membership function circuit in SC technique.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

High-speed bipolar MUX modeling and design.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

Evaluation of power consumption in adiabatic circuits.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

1999

High-speed voltage buffers for the experimental characterization of CMOS transconductance operational amplifiers.

[BibT_eX]

[DOI]

IEEE Trans. Instrum. Meas., 1999

Highly accurate and simple models for CML and ECL gates.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999

A general HDL-A model of a DC-DC switching regulator core.

[BibT_eX]

[DOI]

Davide Torrisi

Riccardo Ursino

Proceedings of the 6th IEEE International Conference on Electronics, Circuits and Systems, 1999

A class AB CMOS current mirror with low-voltage capability.

[BibT_eX]

[DOI]

Proceedings of the 6th IEEE International Conference on Electronics, Circuits and Systems, 1999

Performance parameters of current operational amplifiers.

[BibT_eX]

[DOI]

Proceedings of the 6th IEEE International Conference on Electronics, Circuits and Systems, 1999

1998

High-drive CMOS current amplifier.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 1998

Harmonic distortion in non-linear amplifier with non-linear feedback.

[BibT_eX]

[DOI]

Int. J. Circuit Theory Appl., 1998

A novel fully adjustable CMOS current Schmitt trigger with a 1·5 V power supply.

[BibT_eX]

[DOI]

Int. J. Circuit Theory Appl., 1998

A technique for the reduction of the input resistance of current-mode circuits.

[BibT_eX]

[DOI]

Proceedings of the 5th IEEE International Conference on Electronics, Circuits and Systems, 1998

A high-performance CMOS voltage follower.

[BibT_eX]

[DOI]

Proceedings of the 5th IEEE International Conference on Electronics, Circuits and Systems, 1998

A 1.5 V CMOS voltage multiplier.

[BibT_eX]

[DOI]

Proceedings of the 5th IEEE International Conference on Electronics, Circuits and Systems, 1998

Design of CML gate with the best propagation delay.

[BibT_eX]

[DOI]

Proceedings of the 5th IEEE International Conference on Electronics, Circuits and Systems, 1998

A Novel 1.5-V Cmos Mixer.

[BibT_eX]

[DOI]

Proceedings of the 8th Great Lakes Symposium on VLSI (GLS-VLSI '98), 1998

Novel Simple Models Of Cml Propagation Delay.

[BibT_eX]

[DOI]

Proceedings of the 8th Great Lakes Symposium on VLSI (GLS-VLSI '98), 1998

1996

Area-efficient design of three- and four-stage voltage multipliers for power integrated circuits.

[BibT_eX]

[DOI]

Int. J. Circuit Theory Appl., 1996

Low harmonic distortion class AB CMOS current output stage.

[BibT_eX]

[DOI]

Proceedings of Third International Conference on Electronics, Circuits, and Systems, 1996

Simplified model of an amplifier with two poles and a pole-zero doublet.

[BibT_eX]

[DOI]

Proceedings of Third International Conference on Electronics, Circuits, and Systems, 1996

1995

An Area Efficient Current limiter for Automotive IC: Analysis and Design.

[BibT_eX]

[DOI]

J. Circuits Syst. Comput., 1995

A simple cmos CCII+.

[BibT_eX]

[DOI]

Int. J. Circuit Theory Appl., 1995

A schmitt trigger by means of a ccii+.

[BibT_eX]

[DOI]

G. Diutaldo

Int. J. Circuit Theory Appl., 1995

A CMOS CCII+.

[BibT_eX]

[DOI]

Proceedings of the 1995 IEEE International Symposium on Circuits and Systems, ISCAS 1995, Seattle, Washington, USA, April 30, 1995

1994

Cmos current comparator: Simplified analysis of the delay time.

[BibT_eX]

[DOI]

Int. J. Circuit Theory Appl., 1994

A high-frequency differential sc integrator with highly accurate gain compensation.

[BibT_eX]

[DOI]

Victor da Fonte Dias

Int. J. Circuit Theory Appl., 1994

Improved dynamic model of double and triple charge pumps to take current leakage into account.

[BibT_eX]

[DOI]

Int. J. Circuit Theory Appl., 1994

Double and triple charge pumps with mos diodes: Dynamic models to an optimized design.

[BibT_eX]

[DOI]

Int. J. Circuit Theory Appl., 1994

Design of the Wilson and Improved Wilson MOS Current Mirrors to Reach the Best Settling time.

[BibT_eX]

[DOI]

Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994

A High-Accuracy High-Speed CMOS Current Comparator.

[BibT_eX]

[DOI]

Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994

Optimized Design of 4 Stage Dickson Voltage Multiplier.

[BibT_eX]

[DOI]

Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994

1993

New CMOS current mirrors with improved high-frequency response.

[BibT_eX]

[DOI]