Fu-Wei Chen

According to our database, Fu-Wei Chen authored at least 10 papers between 2008 and 2019.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2019

Crosstalk-aware TSV-buffer Insertion in 3D IC.

Yen-Hao Chen, Po-Chen Huang, Fu-Wei Chen, Allen C.-H. Wu, TingTing Hwang

Proceedings of the 32nd IEEE International System-on-Chip Conference, 2019

2014

Clock-Tree Synthesis with Methodology of Reuse in 3D-IC.

Fu-Wei Chen, TingTing Hwang

ACM J. Emerg. Technol. Comput. Syst., 2014

Fault-tolerant TSV by using scan-chain test TSV.

Fu-Wei Chen, Hui-Ling Ting, TingTing Hwang

Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014

2012

A Physical-Location-Aware X-Bit Redistribution for Maximum IR-Drop Reduction.

Fu-Wei Chen, Shih-Liang Chen, Yung-Sheng Lin, TingTing Hwang

IEEE Trans. Very Large Scale Integr. Syst., 2012

Clock tree synthesis with methodology of re-use in 3D IC.

Fu-Wei Chen, TingTing Hwang

Proceedings of the 49th Annual Design Automation Conference 2012, 2012

2011

A physical-location-aware fault redistribution for maximum IR-drop reduction.

Fu-Wei Chen, Shih-Liang Chen, Yung-Sheng Lin, TingTing Hwang

Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011

2010

Performance-Driven Dual-Rail Routing Architecture for Structured ASIC Design Style.

Fu-Wei Chen, Yi-Yu Liu

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010

2009

Buffer design and optimization for lut-based structured ASIC design styles.

Po-Yang Hsu, Shu-Ting Lee, Fu-Wei Chen, Yi-Yu Liu

Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, 2009

Performance-driven dual-rail insertion for chip-level pre-fabricated design.

Fu-Wei Chen, Yi-Yu Liu

Proceedings of the Design, Automation and Test in Europe, 2009

2008

Wire Sizing Alternative - An Uniform Dual-rail Routing Architecture.

Fu-Wei Chen, Yi-Yu Liu

Proceedings of the Design, Automation and Test in Europe, 2008