Yi-Yu Liu

According to our database, Yi-Yu Liu authored at least 21 papers between 2001 and 2023.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2023

Enhanced and Efficient Guiding Template Design for Lamellar DSA With Graph Monomorphism.

Yi-Sian Ciou, An-Jie Shih, Shao-Yun Fang, Yi-Yu Liu

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., November, 2023

ILP-based Substrate Routing with Mismatched Via Dimension Consideration for Wire-bonding FBGA Package Design.

Jun-Sheng Wu, Chi-An Pan, Yi-Yu Liu

ACM Trans. Design Autom. Electr. Syst., September, 2023

2021

TSE: Two-Step Elimination for MLC STT-RAM Last-Level Cache.

Jen-Wei Hsieh, Yi-Yu Liu, Hung-Tse Lee, Tai Chang

IEEE Trans. Computers, 2021

2020

Guiding Template Design for Lamellar DSA with Multiple Patterning and Self-Aligned Via Process.

An-Jie Shih, Shao-Yun Fang, Yi-Yu Liu

Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020

2017

A Novel Cache-Utilization-Based Dynamic Voltage-Frequency Scaling Mechanism for Reliability Enhancements.

Yen-Hao Chen, Yi-Lun Tang, Yi-Yu Liu, Allen C.-H. Wu, TingTing Hwang

IEEE Trans. Very Large Scale Integr. Syst., 2017

2016

A novel cache-utilization based dynamic voltage frequency scaling (DVFS) mechanism for reliability enhancements.

Yen-Hao Chen, Yi-Lun Tang, Yi-Yu Liu, Allen C.-H. Wu, TingTing Hwang

Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

2014

Buffer Design and Assignment for Structured ASIC.

Po-Yang Hsu, Yi-Yu Liu

J. Inf. Sci. Eng., 2014

Hybrid LUT and SOP Reconfigurable Architecture.

Po-Yang Hsu, Yung-Chih Chen, Yi-Yu Liu

J. Inf. Sci. Eng., 2014

2013

Routability optimization for crossbar-switch structured ASIC design.

Mei-Hsiang Tsai, Po-Yang Hsu, Hung-Yi Li, Yi-Huang Hung, Yi-Yu Liu

ACM Trans. Design Autom. Electr. Syst., 2013

Memory management for dual-addressing memory architecture.

Ting-Wei Hung, Yen-Hao Chen, Yi-Yu Liu

IEICE Electron. Express, 2013

Dual-addressing memory architecture for two-dimensional memory access patterns.

Yen-Hao Chen, Yi-Yu Liu

Proceedings of the Design, Automation and Test in Europe, 2013

2010

Performance-Driven Dual-Rail Routing Architecture for Structured ASIC Design Style.

Fu-Wei Chen, Yi-Yu Liu

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010

Identifying Prostate Cancer-Related Networks from Microarray Data Based on Genotype-Phenotype Networks Using Markov Blanket Search.

Hsiang-Yuan Yeh, Yi-Yu Liu, Cheng-Yu Yeh, Von-Wun Soo

Proceedings of the 10th IEEE International Conference on Bioinformatics and Bioengineering, 2010

2009

Buffer design and optimization for lut-based structured ASIC design styles.

Po-Yang Hsu, Shu-Ting Lee, Fu-Wei Chen, Yi-Yu Liu

Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, 2009

Performance-driven dual-rail insertion for chip-level pre-fabricated design.

Fu-Wei Chen, Yi-Yu Liu

Proceedings of the Design, Automation and Test in Europe, 2009

2008

Wire Sizing Alternative - An Uniform Dual-rail Routing Architecture.

Fu-Wei Chen, Yi-Yu Liu

Proceedings of the Design, Automation and Test in Europe, 2008

2007

Crosstalk-Aware Domino-Logic Synthesis.

Yi-Yu Liu, TingTing Hwang

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007

2006

Crosstalk minimization in logic synthesis for PLAs.

Yi-Yu Liu, Kuo-Hua Wang, TingTing Hwang

ACM Trans. Design Autom. Electr. Syst., 2006

2004

Crosstalk Minimization in Logic Synthesis for PLA.

Yi-Yu Liu, Kuo-Hua Wang, TingTing Hwang

Proceedings of the 2004 Design, 2004

2001

Binary decision diagram with minimum expected path length.

Yi-Yu Liu, Kuo-Hua Wang, TingTing Hwang, C. L. Liu

Proceedings of the Conference on Design, Automation and Test in Europe, 2001

A construction of minimal delay Steiner tree using two-pole delay model.

LiYi Lin, Yi-Yu Liu, TingTing Hwang

Proceedings of ASP-DAC 2001, 2001