Po-Yang Hsu

According to our database, Po-Yang Hsu authored at least 10 papers between 2009 and 2021.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2021

A 7nm 5G Mobile SoC Featuring a 3.0GHz Tri-Gear Application Processor Subsystem.

HsinChen Chen, Rolf Lagerquist, Ashish Nayak, Hugh Mair, Gokulakrishnan Manoharan, Ericbill Wang, Gordon Gammie, Efron Ho, Anand Rajagopalan, Lee-Kee Yong, Ramu Madhavaram, Madhur Jagota, Chi-Jui Chung, Sudhakar Maruthi, Jenny Wiedemeier, Tao Chen, Henry Hsieh, Daniel Dia, Amjad Sikiligiri, Manzur Rahman, Barry Chen, Curtis Lin, Vincent Lin, Elly Chiang, Cheng-Yuh Wu, Po-Yang Hsu, Jason Tsai, Wade Wu, Achuta Thippana, S. A. Huang

Proceedings of the IEEE International Solid-State Circuits Conference, 2021

2015

Reducing the Standby Power Consumption of the S3 State for PCs.

Te Huang, Ying-Wen Bai, Po-Yang Hsu

IEICE Trans. Electron., 2015

2014

Stacking Signal TSV for Thermal Dissipation in Global Routing for 3-D IC.

Po-Yang Hsu, Hsien-Te Chen, TingTing Hwang

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014

Buffer Design and Assignment for Structured ASIC.

Po-Yang Hsu, Yi-Yu Liu

J. Inf. Sci. Eng., 2014

Hybrid LUT and SOP Reconfigurable Architecture.

Po-Yang Hsu, Yung-Chih Chen, Yi-Yu Liu

J. Inf. Sci. Eng., 2014

Compaction-free compressed cache for high performance multi-core system.

Po-Yang Hsu, Pei-Lan Lin, TingTing Hwang

Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2014

2013

Routability optimization for crossbar-switch structured ASIC design.

Mei-Hsiang Tsai, Po-Yang Hsu, Hung-Yi Li, Yi-Huang Hung, Yi-Yu Liu

ACM Trans. Design Autom. Electr. Syst., 2013

Thread-criticality aware dynamic cache reconfiguration in multi-core system.

Po-Yang Hsu, TingTing Hwang

Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2013

Stacking signal TSV for thermal dissipation in global routing for 3D IC.

Po-Yang Hsu, Hsien-Te Chen, TingTing Hwang

Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013

2009

Buffer design and optimization for lut-based structured ASIC design styles.

Po-Yang Hsu, Shu-Ting Lee, Fu-Wei Chen, Yi-Yu Liu

Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, 2009