G. K. Sharma
Affiliations:- ABV-Indian Institute of Information Technology and Management, Gwalior, India
According to our database1,
G. K. Sharma
authored at least 60 papers
between 1991 and 2026.
Collaborative distances:
Collaborative distances:
Timeline
Legend:
Book In proceedings Article PhD thesis Dataset OtherLinks
Online presence:
-
on iiitm.ac.in
On csauthors.net:
Bibliography
2026
MCMDA: A continual learning and frugal AI based quality inspection mechanism for edge computing platforms.
Adv. Eng. Informatics, 2026
2024
FS-3DSSN: an efficient few-shot learning for single-stage 3D object detection on point clouds.
Vis. Comput., November, 2024
Low-light DEtection TRansformer (LDETR): object detection in low-light and adverse weather conditions.
Multim. Tools Appl., November, 2024
A Novel Semi-Supervised Learning for Industrial Edge Computing Platforms in Quality Prediction.
SN Comput. Sci., June, 2024
PackMASNet: An information integration approach for quality inspection in industry 5.0.
Expert Syst. Appl., 2024
Adversarial Label Flipping Attack on Supervised Machine Learning-Based HT Detection Systems.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2024
Towards Designing an Energy Efficient Accelerated Sparse Convolutional Neural Network.
Proceedings of the 36th IEEE International Conference on Tools with Artificial Intelligence, 2024
2023
Structural and SCOAP Features Based Approach for Hardware Trojan Detection Using SHAP and Light Gradient Boosting Model.
J. Electron. Test., August, 2023
Microprocess. Microsystems, 2023
A Novel Mechanism for Continual Learning based Predictive Quality Inspection in Smart Manufacturing.
Proceedings of the IEEE Region 10 Conference, 2023
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2023
2022
A CatBoost Based Approach to Detect Label Flipping Poisoning Attack in Hardware Trojan Detection Systems.
J. Electron. Test., December, 2022
Energy efficient logarithmic-based approximate divider for ASIC and FPGA-based implementations.
Microprocess. Microsystems, April, 2022
2021
IEEE Trans. Very Large Scale Integr. Syst., 2021
A Lightweight Robust Logic Locking Technique to Thwart Sensitization and Cone-Based Attacks.
IEEE Trans. Emerg. Top. Comput., 2021
Integr., 2021
READ: A fixed restoring array based accuracy-configurable approximate divider for energy efficiency.
Integr., 2021
Int. J. Ad Hoc Ubiquitous Comput., 2021
A Few Shot Learning based Approach for Hardware Trojan Detection using Deep Siamese CNN.
Proceedings of the 34th International Conference on VLSI Design and 20th International Conference on Embedded Systems, 2021
2020
IEEE Trans. Emerg. Top. Comput., 2020
Bit significance based reconfigurable approximate restoring dividers and square rooters.
Microelectron. J., 2020
New lightweight Anti-SAT block design and obfuscation technique to thwart removal attack.
Integr., 2020
Area and Energy Efficient Approximate Square Rooters for Error Resilient Applications.
Proceedings of the 33rd International Conference on VLSI Design and 19th International Conference on Embedded Systems, 2020
Proceedings of the 2020 24th International Symposium on VLSI Design and Test (VDAT), 2020
2019
Microprocess. Microsystems, 2019
Turkish J. Electr. Eng. Comput. Sci., 2019
Quality Driven Energy Aware Approximated Core Transform Architecture for HEVC Standard.
Proceedings of the VLSI Design and Test - 23rd International Symposium, 2019
2018
New Lightweight Architectures for Secure FSM Design to Thwart Fault Injection and Trojan Attacks.
J. Electron. Test., 2018
An Energy-Efficient Trusted FSM Design Technique to Thwart Fault Injection and Trojan Attacks.
Proceedings of the 31st International Conference on VLSI Design and 17th International Conference on Embedded Systems, 2018
2017
New Light Weight Threshold Voltage Defined Camouflaged Gates for Trustworthy Designs.
J. Electron. Test., 2017
ACM: An Energy-Efficient Accuracy Configurable Multiplier for Error-Resilient Applications.
J. Electron. Test., 2017
2016
Bit-width-aware constant-delay run-time Accuracy Programmable Adder for error-resilient applications.
Microelectron. J., 2016
A quality-aware Energy-scalable Gaussian Smoothing Filter for image processing applications.
Microprocess. Microsystems, 2016
RICO: A low power repetitive iteration CORDIC for DSP applications in portable devices.
J. Syst. Archit., 2016
Proceedings of the 20th International Symposium on VLSI Design and Test, 2016
Proceedings of the 20th International Symposium on VLSI Design and Test, 2016
A block matching algorithm for deriving quality-tunable motion estimation architecture.
Proceedings of the 11th International Conference on Industrial and Information Systems, 2016
Low power signal processing via approximate multiplier for error-resilient applications.
Proceedings of the 11th International Conference on Industrial and Information Systems, 2016
2015
A novel stability and process sensitivity driven model for optimal sized FinFET based SRAM.
Microelectron. Reliab., 2015
New Topology Approach for Future Process, Voltage and Temperature Aware SRAM Using Independently Controlled Double-Gate FinFET.
J. Low Power Electron., 2015
PAID: Process Aware Imprecise DCT Architecture Trading Quality for Energy Efficiency.
J. Low Power Electron., 2015
Proceedings of the 28th International Conference on VLSI Design, 2015
SPAA-Aware 2D Gaussian Smoothing Filter Design Using Efficient Approximation Techniques.
Proceedings of the 28th International Conference on VLSI Design, 2015
2014
Estimation of Optimized Energy and Latency Constraints for Task Allocation in 3d Network on Chip.
CoRR, 2014
Energy and Latency Aware Application Mapping Algorithm & Optimization for Homogeneous 3D Network on Chip.
CoRR, 2014
A New Sensitivity-Driven Process Variation Aware Self-Repairing Low-Power SRAM Design.
Proceedings of the 2014 27th International Conference on VLSI Design, 2014
Operation-aware assist circuit design for improved write performance of FinFET based SRAM.
Proceedings of the 18th International Symposium on VLSI Design and Test, 2014
Energy scalable approximate DCT architecture trading quality via boundary error-resiliency.
Proceedings of the 27th IEEE International System-on-Chip Conference, 2014
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2014
2013
Proceedings of the VLSI Design and Test, 17th International Symposium, 2013
Double-gate FinFET process variation aware 10T SRAM cell topology design and analysis.
Proceedings of the 21st European Conference on Circuit Theory and Design, 2013
2010
An efficient energy- and bandwidth- aware mapping algorithm for regular NoC architecture.
Proceedings of the Third International Workshop on Network on Chip Architectures, 2010
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2010
2009
Appl. Soft Comput., 2009
2007
J. Supercomput., 2007
2006
Proceedings of the Reconfigurable Computing: Architectures and Applications, 2006
2005
Proceedings of the 2005 International Conference on Field Programmable Logic and Applications (FPL), 2005
2003
Equivalent Query Transformer for Semantic Query Optimization in Distributed Computing Environment.
Proceedings of the 21st IASTED International Multi-Conference on Applied Informatics (AI 2003), 2003
2002
Proceedings of the Applied Parallel Computing Advanced Scientific Computing, 2002
1991
Proceedings of the First Great Lakes Symposium on VLSI, 1991