Joseph B. Manzano

Orcid: 0000-0002-6616-0125

Affiliations:
  • Pacific Northwest National Laboratory (PNNL), Richland, USA
  • University of Delaware, Newark, Department of Electrical and Computer Engineering


According to our database1, Joseph B. Manzano authored at least 56 papers between 2003 and 2023.

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Bibliography

2023
The Landscape of Modern Machine Learning: A Review of Machine, Distributed and Federated Learning.
CoRR, 2023

Evaluating Energy Efficiency of GPUs using Machine Learning Benchmarks.
Proceedings of the IEEE International Parallel and Distributed Processing Symposium, 2023

Assessing Risk in High Performance Computing Attacks.
Proceedings of the 9th International Conference on Information Systems Security and Privacy, 2023

Finding Your Niche: An Evolutionary Approach to HPC Topologies.
Proceedings of the IEEE High Performance Extreme Computing Conference, 2023

Denial of Service Attack Detection via Differential Analysis of Generalized Entropy Progressions.
Proceedings of the IEEE International Conference on Cyber Security and Resilience, 2023

Towards On-Chip Learning for Low Latency Reasoning with End-to-End Synthesis.
Proceedings of the 28th Asia and South Pacific Design Automation Conference, 2023

2022
End-to-End Synthesis of Dynamically Controlled Machine Learning Accelerators.
IEEE Trans. Computers, 2022

Bridging Python to Silicon: The SODA Toolchain.
IEEE Micro, 2022

Extending an asynchronous runtime system for high throughput applications: A case study.
J. Parallel Distributed Comput., 2022

SODA Synthesizer: An Open-Source, Multi-Level, Modular, Extensible Compiler from High-Level Frameworks to Silicon.
Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design, 2022

An MLIR-based Compiler Flow for System-Level Design and Hardware Acceleration.
Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design, 2022

From High-Level Frameworks to custom Silicon with SODA.
Proceedings of the 2022 IEEE Hot Chips 34 Symposium, 2022

SO(DA)<sup>2</sup>: End-to-end Generation of Specialized Reconfigurable Architectures (Invited Talk).
Proceedings of the 13th Workshop on Parallel Programming and Run-Time Management Techniques for Many-Core Architectures and 11th Workshop on Design Tools and Architectures for Multicore Embedded Computing Platforms, 2022

The SODA approach: leveraging high-level synthesis for hardware/software co-design and hardware specialization: invited.
Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022

2021
Denial-of-Service Attack Detection via Differential Analysis of Generalized Entropy Progressions.
CoRR, 2021

MAPA: multi-accelerator pattern allocation policy for multi-tenant GPU servers.
Proceedings of the International Conference for High Performance Computing, 2021

LC-MEMENTO: A Memory Model for Accelerated Architectures.
Proceedings of the Languages and Compilers for Parallel Computing, 2021

Automated Generation of Integrated Digital and Spiking Neuromorphic Machine Learning Accelerators.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2021

Towards Automatic and Agile AI/ML Accelerator Design with End-to-End Synthesis.
Proceedings of the 32nd IEEE International Conference on Application-specific Systems, 2021

2020
SODA: a New Synthesis Infrastructure for Agile Hardware Design of Machine Learning Accelerators.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020

On the Marriage of Asynchronous Many Task Runtimes and Big Data: A Glance.
Proceedings of the 27th IEEE International Conference on High Performance Computing, 2020

Invited: Software Defined Accelerators From Learning Tools Environment.
Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020

2019
A Parallel Graph Environment for Real-World Data Analytics Workflows.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

2018
Characterization of the Impact of Soft Errors on Iterative Methods.
Proceedings of the 25th IEEE International Conference on High Performance Computing, 2018

Comparative analysis of soft-error detection strategies: a case study with iterative methods.
Proceedings of the 15th ACM International Conference on Computing Frontiers, 2018

2017
Exploring performance and energy tradeoffs for irregular applications: A case study on the Tilera many-core architecture.
J. Parallel Distributed Comput., 2017

User-transparent Distributed TensorFlow.
CoRR, 2017

Verification of the Extended Roofline Model for Asynchronous Many Task Runtimes.
Proceedings of the Third International Workshop on Extreme Scale Programming Models and Middleware, 2017

Designing Scalable Distributed Memory Models: A Case Study.
Proceedings of the Computing Frontiers Conference, 2017

2016
Algorithm and Architecture Independent Benchmarking with SEAK.
Proceedings of the 2016 IEEE International Parallel and Distributed Processing Symposium, 2016

Asynchronous Runtimes in Action: An Introspective Framework for a Next Gen Runtime.
Proceedings of the 2016 IEEE International Parallel and Distributed Processing Symposium Workshops, 2016

Extending the Roofline Model for Asynchronous Many-Task Runtimes.
Proceedings of the 2016 IEEE International Conference on Cluster Computing, 2016

Application characterization at scale: lessons learned from developing a distributed open community runtime system for high performance computing.
Proceedings of the ACM International Conference on Computing Frontiers, CF'16, 2016

2015
On the Impact of Execution Models: A Case Study in Computational Chemistry.
Proceedings of the 2015 IEEE International Parallel and Distributed Processing Symposium Workshop, 2015

Gregarious Data Re-structuring in a Many Core Architecture.
Proceedings of the 17th IEEE International Conference on High Performance Computing and Communications, 2015

Locality aware concurrent start for stencil applications.
Proceedings of the 13th Annual IEEE/ACM International Symposium on Code Generation and Optimization, 2015

Optimizing irregular applications for energy and performance on the Tilera many-core architecture.
Proceedings of the 12th ACM International Conference on Computing Frontiers, 2015

Power and performance trade-offs for Space Time Adaptive Processing.
Proceedings of the 26th IEEE International Conference on Application-specific Systems, 2015

2014
Jagged Tiling for Intra-tile Parallelism and Fine-Grain Multithreading.
Proceedings of the Languages and Compilers for Parallel Computing, 2014

ACDT: Architected Composite Data Types trading-in unfettered data access for improved execution.
Proceedings of the 20th IEEE International Conference on Parallel and Distributed Systems, 2014

2012
Fast and Accurate Simulation of the Cray XMT Multithreaded Supercomputer.
IEEE Trans. Parallel Distributed Syst., 2012

The Role of Non-strict Fine-grain Synchronization.
Proceedings of the Transition of HPC Towards Exascale Computing, 2012

2011
OPELL and PM: A Case Study on Porting Shared Memory Programming Models to Accelerators Architectures.
Proceedings of the Languages and Compilers for Parallel Computing, 2011

The elephant and the mice: the role of non-strict fine-grain synchronization for modern many-core architectures.
Proceedings of the 25th International Conference on Supercomputing, 2011, Tucson, AZ, USA, May 31, 2011

2010
A Study of a Software Cache Implementation of the OpenMP Memory Model for Multicore and Manycore Architectures.
Proceedings of the Euro-Par 2010 - Parallel Processing, 16th International Euro-Par Conference, Ischia, Italy, August 31, 2010

2009
TL-DAE: Thread-Level Decoupled Access/Execution for OpenMP on the Cyclops-64 Many-Core Processor.
Proceedings of the Languages and Compilers for Parallel Computing, 2009

Tile Reduction: The First Step towards Tile Aware Parallelization in OpenMP.
Proceedings of the Evolving OpenMP in an Age of Extreme Parallelism, 2009

Tile Percolation: An OpenMP Tile Aware Parallelization Technique for the Cyclops-64 Multicore Processor.
Proceedings of the Euro-Par 2009 Parallel Processing, 2009

2008
A Quantitative Study of the On-Chip Network and Memory Hierarchy Design for Many-Core Processor.
Proceedings of the 14th International Conference on Parallel and Distributed Systems, 2008

2007
Toward an Automatic Code Layout Methodology.
Proceedings of the A Practical Programming Model for the Multi-Core Era, 2007

2006
A User-Friendly Methodology for Automatic Exploration of Compiler Options.
Proceedings of the International Conference on Software Engineering Research and Practice & Conference on Programming Languages and Compilers, 2006

2005
Madd Operation Aware Redundancy Elimination.
Int. J. Softw. Eng. Knowl. Eng., 2005

Identifying Multiply-Add Operations in Kylin Compiler.
Proceedings of The 2005 International Conference on Embedded Systems and Applications, 2005

2004
Software De-Pipelining Technique.
Proceedings of the 4th IEEE International Workshop on Source Code Analysis and Manipulation (SCAM 2004), 2004

Loop optimization with tradeoff between cycle count and code size for DSP applications.
Proceedings of the 2004 12th European Signal Processing Conference, 2004

2003
De-pipeline a software-pipelined loop.
Proceedings of the 2003 IEEE International Conference on Acoustics, 2003


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