Ganesh Lakshminarayana

According to our database1, Ganesh Lakshminarayana authored at least 48 papers between 1996 and 2006.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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Article 
PhD thesis 
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Links

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Bibliography

2006
The LOTTERYBUS on-chip communication architecture.
IEEE Trans. Very Large Scale Integr. Syst., 2006

2005
Memory binding for performance optimization of control-flow intensive behavioral descriptions.
IEEE Trans. Very Large Scale Integr. Syst., 2005

Input space-adaptive optimization for embedded-software synthesis.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005

2004
Input space adaptive design: a high-level methodology for optimizing energy and performance.
IEEE Trans. Very Large Scale Integr. Syst., 2004

Common-case computation: a high-level energy and performance optimization technique.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004

Design of high-performance system-on-chips using communication architecture tuners.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004

2003
Analysis of power dissipation in embedded systems using real-time operating systems.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003

2002
High-level energy macromodeling of embedded software.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002

High-level test compaction techniques.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002

Input Space Adaptive Embedded Software Synthesis.
Proceedings of the ASPDAC 2002 / VLSI Design 2002, 2002

Optimizing public-key encryption for wireless clients.
Proceedings of the IEEE International Conference on Communications, 2002

2001
TAO: regular expression-based register-transfer level testability analysis and optimization.
IEEE Trans. Very Large Scale Integr. Syst., 2001

Testing of core-based systems-on-a-chip.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001

Accurate Power Macro-modeling Techniques for Complex RTL Circuits.
Proceedings of the 14th International Conference on VLSI Design (VLSI Design 2001), 2001

Transient Power Management Through High Level Synthesis.
Proceedings of the 2001 IEEE/ACM International Conference on Computer-Aided Design, 2001

Input Space Adaptive Design: A High-level Methodology for Energy and Performance Optimization.
Proceedings of the 38th Design Automation Conference, 2001

High-level Software Energy Macro-modeling.
Proceedings of the 38th Design Automation Conference, 2001

LOTTERYBUS: A New High-Performance Communication Architecture for System-on-Chip Designs.
Proceedings of the 38th Design Automation Conference, 2001

2000
TAO-BIST: A framework for testability analysis and optimization forbuilt-in self-test of RTL circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000

Integrating variable-latency components into high-level synthesis.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000

Incorporating speculative execution into scheduling ofcontrol-flow-intensive designs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000

Behavioral Synthesis of Fault Secure Controller/Datapaths Based on Aliasing Probability Analysis.
IEEE Trans. Computers, 2000

High-Level Synthesis with Variable-Latency Components.
Proceedings of the 13th International Conference on VLSI Design (VLSI Design 2000), 2000

: Reducing test application time in high-level test generation.
Proceedings of the Proceedings IEEE International Test Conference 2000, 2000

Communication architecture tuners: a methodology for the design of high-performance communication architectures for systems-on-chips.
Proceedings of the 37th Conference on Design Automation, 2000

Power analysis of embedded operating systems.
Proceedings of the 37th Conference on Design Automation, 2000

1999
Power management in high-level synthesis.
IEEE Trans. Very Large Scale Integr. Syst., 1999

COSYN: Hardware-software co-synthesis of heterogeneous distributed embedded systems.
IEEE Trans. Very Large Scale Integr. Syst., 1999

Wavesched: a novel scheduling technique for control-flow intensive designs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999

FACT: a framework for applying throughput and power optimizing transformations to control-flow-intensive behavioral descriptions.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999

High-level synthesis of power-optimized and area-optimized circuits from hierarchical data-flow intensive behaviors.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999

High-level synthesis of low-power control-flow intensive circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999

TAO-BIST: A Framework for Testability Analysis and Optimizationb of RTL Circuits for BIST.
Proceedings of the 17th IEEE VLSI Test Symposium (VTS '99), 1999

A framework for testing core-based systems-on-a-chip.
Proceedings of the 1999 IEEE/ACM International Conference on Computer-Aided Design, 1999

Memory binding for performance optimization of control-flow intensive behaviors.
Proceedings of the 1999 IEEE/ACM International Conference on Computer-Aided Design, 1999

Common-Case Computation: A High-Level Technique for Power and Performance Optimization.
Proceedings of the 36th Conference on Design Automation, 1999

1998
A Power Management Methodology for High-Level Synthesis.
Proceedings of the 11th International Conference on VLSI Design (VLSI Design 1991), 1998

TAO: regular expression based high-level testability analysis and optimization.
Proceedings of the Proceedings IEEE International Test Conference 1998, 1998

Fast high-level power estimation for control-flow intensive design.
Proceedings of the 1998 International Symposium on Low Power Electronics and Design, 1998

Removal of memory access bottlenecks for scheduling control-flow intensive behavioral descriptions.
Proceedings of the 1998 IEEE/ACM International Conference on Computer-Aided Design, 1998

Transforming control-flow intensive designs to facilitate power management.
Proceedings of the 1998 IEEE/ACM International Conference on Computer-Aided Design, 1998

IMPACT: A High-Level Synthesis System for Low Power Control-Flow Intensive Circuits.
Proceedings of the 1998 Design, 1998

Incorporating Speculative Execution into Scheduling of Control-Flow Intensive Behavioral Descriptions.
Proceedings of the 35th Conference on Design Automation, 1998

Synthesis of Power-Optimized and Area-Optimized Circuits from Hierarchical Behavioral Descriptions.
Proceedings of the 35th Conference on Design Automation, 1998

<i>FACT</i>: A Framework for the Application of Throughput and Power Optimizing Transformations to Control-Flow Intensive Behavioral Descriptions.
Proceedings of the 35th Conference on Design Automation, 1998

1997
Wavesched: a novel scheduling technique for control-flow intensive behavioral descriptions.
Proceedings of the 1997 IEEE/ACM International Conference on Computer-Aided Design, 1997

COSYN: Hardware-Software Co-Synthesis of Embedded Systems.
Proceedings of the 34st Conference on Design Automation, 1997

1996
Behavioral Synthesis of Fault Secure Controller?Datapaths using Aliasing Probability Analysis.
Proceedings of the Digest of Papers: FTCS-26, 1996


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