Anand Raghunathan

Trans. Mach. Learn. Res., 2023

Input Compression with Positional Consistency for Efficient Training and Inference of Transformer Neural Networks.

[BibT_eX]

[DOI]

CoRR, 2023

LRMP: Layer Replication with Mixed Precision for Spatial In-memory DNN Accelerators.

[BibT_eX]

[DOI]

CoRR, 2023

Evaluation of STT-MRAM as a Scratchpad for Training in ML Accelerators.

[BibT_eX]

[DOI]

Sourjya Roy

Cheng Wang

CoRR, 2023

EvoSh: Evolutionary Search with Shaving to Enable Power-Latency Tradeoff in Deep Learning Computing on Embedded Systems.

[BibT_eX]

[DOI]

Proceedings of the 36th IEEE International System-on-Chip Conference, 2023

TokenDrop + BucketSampler: Towards Efficient Padding-free Fine-tuning of Language Models.

[BibT_eX]

[DOI]

Proceedings of the Findings of the Association for Computational Linguistics: EMNLP 2023, 2023

2022

Contention Grading and Adaptive Model Selection for Machine Vision in Embedded Systems.

[BibT_eX]

[DOI]

ACM Trans. Embed. Comput. Syst., September, 2022

Compute-in-Memory Technologies and Architectures for Deep Learning Workloads.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2022

Ax-BxP: Approximate Blocked Computation for Precision-reconfigurable Deep Neural Network Acceleration.

[BibT_eX]

[DOI]

Reena Elangovan

ACM Trans. Design Autom. Electr. Syst., 2022

A Co-design view of Compute in-Memory with Non-Volatile Elements for Neural Networks.

[BibT_eX]

[DOI]

CoRR, 2022

STeP-CiM: Strain-enabled Ternary Precision Computation-in-Memory based on Non-Volatile 2D Piezoelectric Transistors.

[BibT_eX]

[DOI]

Niharika Thakuria

Reena Elangovan

CoRR, 2022

Layerwise Disaggregated Evaluation of Spiking Neural Networks.

[BibT_eX]

[DOI]

Proceedings of the ISLPED '22: ACM/IEEE International Symposium on Low Power Electronics and Design, Boston, MA, USA, August 1, 2022

Energy Efficient Cache Design with Piezoelectric FETs.

[BibT_eX]

[DOI]

Proceedings of the ISLPED '22: ACM/IEEE International Symposium on Low Power Electronics and Design, Boston, MA, USA, August 1, 2022

AxFormer: Accuracy-driven Approximation of Transformers for Faster, Smaller and more Accurate NLP Models.

[BibT_eX]

[DOI]

Proceedings of the International Joint Conference on Neural Networks, 2022

Seprox: Sequence-Based Approximations for Compressing Ultra-Low Precision Deep Neural Networks.

[BibT_eX]

[DOI]

Aradhana Mohan Parvathy

Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design, 2022

Approximate Computing and the Efficient Machine Learning Expedition.

[BibT_eX]

[DOI]

Xiaoxuan Yang

Georgios Zervakis

Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design, 2022

A cross-layer approach to cognitive computing: invited.

[BibT_eX]

[DOI]

Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022

Efficient ensembles of graph neural networks.

[BibT_eX]

[DOI]

Jacob R. Stevens

Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022

Efficiency attacks on spiking neural networks.

[BibT_eX]

[DOI]

Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022

Approximate Computing for Machine Learning Workloads: A Circuits and Systems Perspective.

[BibT_eX]

[DOI]

Proceedings of the Approximate Computing, 2022

2021

TxSim: Modeling Training of Deep Neural Networks on Resistive Crossbar Systems.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2021

RxNN: A Framework for Evaluating Deep Neural Networks on Resistive Crossbars.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021

PIM-DRAM: Accelerating Machine Learning Workloads Using Processing in Commodity DRAM.

[BibT_eX]

[DOI]

Sourjya Roy

Mustafa Fayez Ali

IEEE J. Emerg. Sel. Topics Circuits Syst., 2021

HW/SW Framework for Improving the Safety of Implantable and Wearable Medical Devices.

[BibT_eX]

[DOI]

CoRR, 2021

Efficacy of Pruning in Ultra-Low Precision DNNs.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, 2021

Value Similarity Extensions for Approximate Computing in General-Purpose Processors.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

Softermax: Hardware/Software Co-Design of an Efficient Softmax for Transformers.

[BibT_eX]

[DOI]

Jacob R. Stevens

Steve Dai

Brucek Khailany

Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021

GNNerator: A Hardware/Software Framework for Accelerating Graph Neural Networks.

[BibT_eX]

[DOI]

Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021

Contention-aware Adaptive Model Selection for Machine Vision in Embedded Systems.

[BibT_eX]

[DOI]

Proceedings of the 3rd IEEE International Conference on Artificial Intelligence Circuits and Systems, 2021

Design Tools for Resistive Crossbar based Machine Learning Accelerators.

[BibT_eX]

[DOI]

Proceedings of the 3rd IEEE International Conference on Artificial Intelligence Circuits and Systems, 2021

2020

Approximate Memory Compression.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2020

TiM-DNN: Ternary In-Memory Accelerator for Deep Neural Networks.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2020

CxDNN: Hardware-software Compensation Methods for Deep Neural Networks on Resistive Crossbar Systems.

[BibT_eX]

[DOI]

ACM Trans. Embed. Comput. Syst., 2020

DyVEDeep: Dynamic Variable Effort Deep Neural Networks.

[BibT_eX]

[DOI]

Sanjay Ganapathy

Giridhur Sriraman

ACM Trans. Embed. Comput. Syst., 2020

Logic Synthesis of Approximate Circuits.

[BibT_eX]

[DOI]

Amit Sabne

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

Sparsity Turns Adversarial: Energy and Latency Attacks on Deep Neural Networks.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

Resistive Crossbars as Approximate Hardware Building Blocks for Machine Learning: Opportunities and Challenges.

[BibT_eX]

[DOI]

Proc. IEEE, 2020

Optimizing Transformers with Approximate Computing for Faster, Smaller and more Accurate NLP Models.

[BibT_eX]

[DOI]

CoRR, 2020

Adversarial Sparsity Attacks on Deep Neural Networks.

[BibT_eX]

[DOI]

CoRR, 2020

Gradual Channel Pruning While Training Using Feature Relevance Scores for Convolutional Neural Networks.

[BibT_eX]

[DOI]

IEEE Access, 2020

Pruning Filters while Training for Efficiently Optimizing Deep Learning Networks.

[BibT_eX]

[DOI]

Sourjya Roy

Gopalakrishnan Srinivasan

Proceedings of the 2020 International Joint Conference on Neural Networks, 2020

A Case for Generalizable DNN Cost Models for Mobile Devices.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Workload Characterization, 2020

EMPIR: Ensembles of Mixed Precision Deep Networks for Increased Robustness Against Adversarial Attacks.

[BibT_eX]

[DOI]

Proceedings of the 8th International Conference on Learning Representations, 2020

Ternary Compute-Enabled Memory using Ferroelectric Transistors for Accelerating Deep Neural Networks.

[BibT_eX]

[DOI]

Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

Communication-efficient View-Pooling for Distributed Multi-View Neural Networks.

[BibT_eX]

[DOI]

Manik Singhal

Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

Sparsity-Aware Caches to Accelerate Deep Neural Networks.

[BibT_eX]

[DOI]

Kamakoti Veezhinathan

Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

Emerging Neural Workloads and Their Impact on Hardware.

[BibT_eX]

[DOI]

Ann Franchesca Laguna

Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

2019

SparCE: Sparsity Aware General-Purpose Core Extensions to Accelerate Deep Neural Networks.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2019

Neural network accelerator design with resistive crossbars: Opportunities and challenges.

[BibT_eX]

[DOI]

IBM J. Res. Dev., 2019

Valley-Coupled-Spintronic Non-Volatile Memories with Compute-In-Memory Support.

[BibT_eX]

[DOI]

CoRR, 2019

Manna: An Accelerator for Memory-Augmented Neural Networks.

[BibT_eX]

[DOI]

Proceedings of the 52nd Annual IEEE/ACM International Symposium on Microarchitecture, 2019

Non-Volatile Memory utilizing Reconfigurable Ferroelectric Transistors to enable Differential Read and Energy-Efficient In-Memory Computation.

[BibT_eX]

[DOI]

Proceedings of the 2019 IEEE/ACM International Symposium on Low Power Electronics and Design, 2019

Dynamic Spike Bundling for Energy-Efficient Spiking Neural Networks.

[BibT_eX]

[DOI]

Proceedings of the 2019 IEEE/ACM International Symposium on Low Power Electronics and Design, 2019

Data Subsetting: A Data-Centric Approach to Approximate Computing.

[BibT_eX]

[DOI]

Nitin Chandrachoodan

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

X-MANN: A Crossbar based Architecture for Memory Augmented Neural Networks.

[BibT_eX]

[DOI]

Proceedings of the 56th Annual Design Automation Conference 2019, 2019

Pack and Detect: Fast Object Detection in Videos Using Region-of-Interest Packing.

[BibT_eX]

[DOI]

Athindran Ramesh Kumar

Proceedings of the ACM India Joint International Conference on Data Science and Management of Data, 2019

Automatic Synthesis Techniques for Approximate Circuits.

[BibT_eX]

[DOI]

Proceedings of the Approximate Circuits, Methodologies and CAD., 2019

2018

Computing in Memory With Spin-Transfer Torque Magnetic RAM.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2018

Approximate Computing for Long Short Term Memory (LSTM) Neural Networks.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

Energy-Efficient Neural Computing with Approximate Multipliers.

[BibT_eX]

[DOI]

Aayush Ankit

ACM J. Emerg. Technol. Comput. Syst., 2018

Energy Efficient Neural Computing: A Study of Cross-Layer Approximations.

[BibT_eX]

[DOI]

Gopalakrishnan Srinivasan

IEEE J. Emerg. Sel. Topics Circuits Syst., 2018

A Quality-Configurable Approximate Serial Bus for Energy-Efficient Sensory Data Transfer.

[BibT_eX]

[DOI]

IEEE J. Emerg. Sel. Topics Circuits Syst., 2018

Guest Editors' Introduction.

[BibT_eX]

[DOI]

Sybille Hellebrand

Jörg Henkel

Hans-Joachim Wunderlich

IEEE Embed. Syst. Lett., 2018

Rx-Caffe: Framework for evaluating and training Deep Neural Networks on Resistive Crossbars.

[BibT_eX]

[DOI]

CoRR, 2018

SYNCVIBE: Fast and Secure Device Pairing through Physical Vibration on Commodity Smartphones.

[BibT_eX]

[DOI]

Proceedings of the 36th IEEE International Conference on Computer Design, 2018

AxBA: an approximate bus architecture framework.

[BibT_eX]

[DOI]

Jacob R. Stevens

Proceedings of the International Conference on Computer-Aided Design, 2018

ACCLIB: Accelerators as libraries.

[BibT_eX]

[DOI]

Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

Computing-in-memory with spintronics.

[BibT_eX]

[DOI]

Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

2017

Energy-Efficient Reduce-and-Rank Using Input-Adaptive Approximations.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2017

Energy-Efficient Object Detection Using Semantic Decomposition.

[BibT_eX]

[DOI]

Abhronil Sengupta

IEEE Trans. Very Large Scale Integr. Syst., 2017

Approximate Error Detection With Stochastic Checkers.

[BibT_eX]

[DOI]

Neel Gala

V. Kamakoti

IEEE Trans. Very Large Scale Integr. Syst., 2017

DISASTER: Dedicated Intelligent Security Attacks on Sensor-Triggered Emergency Responses.

[BibT_eX]

[DOI]

IEEE Trans. Multi Scale Comput. Syst., 2017

Wearable Medical Sensor-Based System Design: A Survey.

[BibT_eX]

[DOI]

IEEE Trans. Multi Scale Comput. Syst., 2017

Design and Management of Battery-Supercapacitor Hybrid Electrical Energy Storage Systems for Regulation Services.

[BibT_eX]

[DOI]

Younghyun Kim

IEEE Trans. Multi Scale Comput. Syst., 2017

CABA: Continuous Authentication Based on BioAura.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2017

DyVEDeep: Dynamic Variable Effort Deep Neural Networks.

[BibT_eX]

[DOI]

Sanjay Ganapathy

CoRR, 2017

Model-based Iterative CT Image Reconstruction on GPUs.

[BibT_eX]

[DOI]

Proceedings of the 22nd ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, 2017

A Programmable Event-driven Architecture for Evaluating Spiking Neural Networks.

[BibT_eX]

[DOI]

Arnab Roy

Neel Gala

Kamakoti Veezhinathan

Proceedings of the 2017 IEEE/ACM International Symposium on Low Power Electronics and Design, 2017

Approximate memory compression for energy-efficiency.

[BibT_eX]

[DOI]

Proceedings of the 2017 IEEE/ACM International Symposium on Low Power Electronics and Design, 2017

AXSERBUS: A quality-configurable approximate serial bus for energy-efficient sensing.

[BibT_eX]

[DOI]

Proceedings of the 2017 IEEE/ACM International Symposium on Low Power Electronics and Design, 2017

ScaleDeep: A Scalable Compute Architecture for Learning and Evaluating Deep Networks.

[BibT_eX]

[DOI]

Proceedings of the 44th Annual International Symposium on Computer Architecture, 2017

Approximate computing for spiking neural networks.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

STAxCache: An approximate, energy efficient STT-MRAM cache.

[BibT_eX]

[DOI]

Zoha Pajouhi

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

A Pathway to Enable Exponential Scaling for the Beyond-CMOS Era: Invited.

[BibT_eX]

[DOI]

Proceedings of the 54th Annual Design Automation Conference, 2017

2016

EMBIRA: An Accelerator for Model-Based Iterative Reconstruction.

[BibT_eX]

[DOI]

Junshi Liu

Singanallur V. Venkatakrishnan

Yun Pan

Charles A. Bouman

IEEE Trans. Very Large Scale Integr. Syst., 2016

Emulation-Based Analysis of System-on-Chip Performance Under Variations.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2016

Embedding Read-Only Memory in Spin-Transfer Torque MRAM-Based On-Chip Caches.

[BibT_eX]

[DOI]

Dongsoo Lee

IEEE Trans. Very Large Scale Integr. Syst., 2016

Physiological Information Leakage: A New Frontier in Health Information Security.

[BibT_eX]

[DOI]

IEEE Trans. Emerg. Top. Comput., 2016

Spin-Transfer Torque Devices for Logic and Memory: Prospects and Perspectives.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016

Cache Design with Domain Wall Memory.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2016

Spin-Transfer Torque Memories: Devices, Circuits, and Systems.

[BibT_eX]

[DOI]

Yusung Kim

Sri Harsha Choday

Proc. IEEE, 2016

Yield, Area, and Energy Optimization in STT-MRAMs Using Failure-Aware ECC.

[BibT_eX]

[DOI]

ACM J. Emerg. Technol. Comput. Syst., 2016

Asymmetric Underlapped FinFETs for Near- and Super-Threshold Logic at Sub-10nm Technology Nodes.

[BibT_eX]

[DOI]

A. Arun Goud

ACM J. Emerg. Technol. Comput. Syst., 2016

Integrated Systems in the More-Than-Moore Era: Designing Low-Cost Energy-Efficient Systems Using Heterogeneous Components.

[BibT_eX]

[DOI]

IEEE Des. Test, 2016

Approximate Computing.

[BibT_eX]

[DOI]

Proceedings of the 29th International Conference on VLSI Design and 15th International Conference on Embedded Systems, 2016

Neuromorphic Computing Enabled by Spin-Transfer Torque Devices.

[BibT_eX]

[DOI]

Proceedings of the 29th International Conference on VLSI Design and 15th International Conference on Embedded Systems, 2016

High performance model based image reconstruction.

[BibT_eX]

[DOI]

Proceedings of the 21st ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, 2016

STOCK: Stochastic Checkers for Low-overhead Approximate Error Detection.

[BibT_eX]

[DOI]

Neel Gala

V. Kamakoti

Proceedings of the 2016 International Symposium on Low Power Electronics and Design, 2016

Multiplier-less Artificial Neurons exploiting error resiliency for energy-efficient neural computing.

[BibT_eX]

[DOI]

Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

Approximation through logic isolation for the design of quality configurable circuits.

[BibT_eX]

[DOI]

Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

Invited - Cross-layer approximations for neuromorphic computing: from devices to circuits and systems.

[BibT_eX]

[DOI]

Abhronil Sengupta

Gopalakrishnan Srinivasan

Proceedings of the 53rd Annual Design Automation Conference, 2016

Designing approximate circuits using clock overgating.

[BibT_eX]

[DOI]

Proceedings of the 53rd Annual Design Automation Conference, 2016

Efficient embedded learning for IoT devices.

[BibT_eX]

[DOI]

Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016

2015

Joint Work and Voltage/Frequency Scaling for Quality-Optimized Dynamic Thermal Management.

[BibT_eX]

[DOI]

Ali Mirtar

IEEE Trans. Very Large Scale Integr. Syst., 2015

An Application Adaptation Approach to Mitigate the Impact of Dynamic Thermal Management on Video Encoding.

[BibT_eX]

[DOI]

Ali Mirtar

ACM Trans. Design Autom. Electr. Syst., 2015

Energy-Efficient Long-term Continuous Personal Health Monitoring.

[BibT_eX]

[DOI]

Arsalan Mohsen Nia

Susmita Sur-Kolay

IEEE Trans. Multi Scale Comput. Syst., 2015

Systematic Poisoning Attacks on and Defenses for Machine Learning in Healthcare.

[BibT_eX]

[DOI]

Susmita Sur-Kolay

IEEE J. Biomed. Health Informatics, 2015

Exploring Spin-Transfer-Torque Devices for Logic Applications.

[BibT_eX]

[DOI]

Zoha Pajouhi

Karthik Yogendra

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015

Energy-Efficient All-Spin Cache Hierarchy Using Shift-Based Writes and Multilevel Storage.

[BibT_eX]

[DOI]

ACM J. Emerg. Technol. Comput. Syst., 2015

Object Detection using Semantic Decomposition for Energy-Efficient Neural Computing.

[BibT_eX]

[DOI]

Abhronil Sengupta

CoRR, 2015

Approximate Computing: An Energy-Efficient Computing Technique for Error Resilient Applications.

[BibT_eX]

[DOI]

Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015

Spintastic: spin-based stochastic logic for energy-efficient computing.

[BibT_eX]

[DOI]

Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

Computing approximately, and efficiently.

[BibT_eX]

[DOI]

Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

DyReCTape: a dynamically reconfigurable cache using domain wall memory tapes.

[BibT_eX]

[DOI]

Vijay S. Pai

Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

Quality configurable reduce-and-rank for energy efficient approximate computing.

[BibT_eX]

[DOI]

Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

Asymmetric underlapped FinFET based robust SRAM design at 7nm node.

[BibT_eX]

[DOI]

A. Arun Goud

Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

Scalable-effort classifiers for energy-efficient machine learning.

[BibT_eX]

[DOI]

Jie Liu

Mohammed Shoaib

Proceedings of the 52nd Annual Design Automation Conference, 2015

Approximate computing and the quest for computing efficiency.

[BibT_eX]

[DOI]

Proceedings of the 52nd Annual Design Automation Conference, 2015

Approximate storage for energy efficient spintronic memories.

[BibT_eX]

[DOI]

Proceedings of the 52nd Annual Design Automation Conference, 2015

Vibration-based secure side channel for medical devices.

[BibT_eX]

[DOI]

Proceedings of the 52nd Annual Design Automation Conference, 2015

2014

Scalable Effort Hardware Design.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2014

Trustworthiness of Medical Devices and Body Area Networks.

[BibT_eX]

[DOI]

Proc. IEEE, 2014

A defense framework against malware and vulnerability exploits.

[BibT_eX]

[DOI]

Int. J. Inf. Sec., 2014

STT-SNN: A Spin-Transfer-Torque Based Soft-Limiting Non-Linear Neuron for Low-Power Artificial Neural Networks.

[BibT_eX]

[DOI]

CoRR, 2014

ShuffleWatcher: Shuffle-aware Scheduling in Multi-tenant MapReduce Clusters.

[BibT_eX]

[DOI]

Proceedings of the 2014 USENIX Annual Technical Conference, 2014

AxNN: energy-efficient neuromorphic systems using approximate computing.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Low Power Electronics and Design, 2014

SPINDLE: SPINtronic deep learning engine for large-scale neuromorphic computing.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Low Power Electronics and Design, 2014

Variation tolerant design of a vector processor for recognition, mining and synthesis.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Low Power Electronics and Design, 2014

StoRM: a stochastic recognition and mining processor.

[BibT_eX]

[DOI]

Vinay K. Chippa

Proceedings of the International Symposium on Low Power Electronics and Design, 2014

STAG: Spintronic-Tape Architecture for GPGPU cache hierarchies.

[BibT_eX]

[DOI]

Proceedings of the ACM/IEEE 41st International Symposium on Computer Architecture, 2014

Design and management of hybrid electrical energy storage systems for regulation services.

[BibT_eX]

[DOI]

Younghyun Kim

Proceedings of the International Green Computing Conference, 2014

Approximate computing for efficient information processing.

[BibT_eX]

[DOI]

Proceedings of the 12th IEEE Symposium on Embedded Systems for Real-time Multimedia, 2014

ASLAN: Synthesis of approximate sequential circuits.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

Variation Aware Cache Partitioning for Multithreaded Programs.

[BibT_eX]

[DOI]

Proceedings of the 51st Annual Design Automation Conference 2014, 2014

2013

Managing the Quality vs. Efficiency Trade-off Using Dynamic Effort Scaling.

[BibT_eX]

[DOI]

ACM Trans. Embed. Comput. Syst., 2013

Low-Power Digital Signal Processing Using Approximate Adders.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013

MedMon: Securing Medical Devices Through Wireless Monitoring and Anomaly Detection.

[BibT_eX]

[DOI]

IEEE Trans. Biomed. Circuits Syst., 2013

Improving the Trustworthiness of Medical Device Software with Formal Verification Methods.

[BibT_eX]

[DOI]

IEEE Embed. Syst. Lett., 2013

Energy-efficient and Secure Sensor Data Transmission Using Encompression.

[BibT_eX]

[DOI]

Proceedings of the 26th International Conference on VLSI Design and 12th International Conference on Embedded Systems, 2013

Emerging Frontiers in Embedded Security.

[BibT_eX]

[DOI]

Proceedings of the 26th International Conference on VLSI Design and 12th International Conference on Embedded Systems, 2013

Localized Heating for Building Energy Efficiency.

[BibT_eX]

[DOI]

Proceedings of the 26th International Conference on VLSI Design and 12th International Conference on Embedded Systems, 2013

Reading spin-torque memory with spin-torque sensors.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2013

Quality programmable vector processors for approximate computing.

[BibT_eX]

[DOI]

Proceedings of the 46th Annual IEEE/ACM International Symposium on Microarchitecture, 2013

Multi-level magnetic RAM using domain wall shift for energy-efficient, high-density caches.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED), 2013

Approximate computing: Energy-efficient computing with good-enough results.

[BibT_eX]

[DOI]

Proceedings of the 2013 IEEE 19th International On-Line Testing Symposium (IOLTS), 2013

DWM-TAPESTRI - an energy efficient all-spin cache using domain wall shift based writes.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2013

Substitute-and-simplify: a unified design paradigm for approximate and quality configurable circuits.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2013

Towards trustworthy medical devices and body area networks.

[BibT_eX]

[DOI]

Proceedings of the 50th Annual Design Automation Conference 2013, 2013

Relax-and-retime: a methodology for energy-efficient recovery based design.

[BibT_eX]

[DOI]

Adithya Parandhaman

Proceedings of the 50th Annual Design Automation Conference 2013, 2013

Analysis and characterization of inherent application resilience for approximate computing.

[BibT_eX]

[DOI]

Proceedings of the 50th Annual Design Automation Conference 2013, 2013

Energy-efficient recognition and mining processor using scalable effort design.

[BibT_eX]

[DOI]

Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013

Approximate computing: An integrated hardware approach.

[BibT_eX]

[DOI]

Vinay K. Chippa

Proceedings of the 2013 Asilomar Conference on Signals, 2013

2012

CLIP: Circuit Level IC Protection Through Direct Injection of Process Variations.

[BibT_eX]

[DOI]

W. Paul Griffin

IEEE Trans. Very Large Scale Integr. Syst., 2012

Variation-Aware Voltage Level Selection.

[BibT_eX]

[DOI]

Saumya Chandra

IEEE Trans. Very Large Scale Integr. Syst., 2012

A Trusted Virtual Machine in an Untrusted Management Environment.

[BibT_eX]

[DOI]

IEEE Trans. Serv. Comput., 2012

Secure reconfiguration of software-defined radio.

[BibT_eX]

[DOI]

ACM Trans. Embed. Comput. Syst., 2012

INVISIOS: A Lightweight, Minimally Intrusive Secure Execution Environment.

[BibT_eX]

[DOI]

ACM Trans. Embed. Comput. Syst., 2012

Guest Editors' Introduction: Green Buildings.

[BibT_eX]

[DOI]

Yuvraj Agarwal

IEEE Des. Test Comput., 2012

Automatic generation of software pipelines for heterogeneous parallel systems.

[BibT_eX]

[DOI]

Jacques A. Pienaar

Proceedings of the SC Conference on High Performance Computing Networking, 2012

TapeCache: a high density, energy efficient cache based on domain wall memory.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Low Power Electronics and Design, 2012

Adaptation of video encoding to address dynamic thermal management effects.

[BibT_eX]

[DOI]

Ali Mirtar

Proceedings of the 2012 International Green Computing Conference, 2012

Functional analysis of circuits under timing variations.

[BibT_eX]

[DOI]

Proceedings of the 17th IEEE European Test Symposium, 2012

On Modeling and Evaluation of Logic Circuits under Timing Variations.

[BibT_eX]

[DOI]

Proceedings of the 15th Euromicro Conference on Digital System Design, 2012

SALSA: systematic logic synthesis of approximate circuits.

[BibT_eX]

[DOI]

Amit Sabne

Proceedings of the 49th Annual Design Automation Conference 2012, 2012

Future cache design using STT MRAMs for improved energy efficiency: devices, circuits and architecture.

[BibT_eX]

[DOI]

Sang Phill Park

Niladri Narayan Mojumder

Proceedings of the 49th Annual Design Automation Conference 2012, 2012

Recovery-based design for variation-tolerant SoCs.

[BibT_eX]

[DOI]

Proceedings of the 49th Annual Design Automation Conference 2012, 2012

PIC: Partitioned Iterative Convergence for Clusters.

[BibT_eX]

[DOI]

Proceedings of the 2012 IEEE International Conference on Cluster Computing, 2012

Tarazu: optimizing MapReduce on heterogeneous clusters.

[BibT_eX]

[DOI]

Proceedings of the 17th International Conference on Architectural Support for Programming Languages and Operating Systems, 2012

2011

A framework for defending embedded systems against software attacks.

[BibT_eX]

[DOI]

Najwa Aaraj

ACM Trans. Embed. Comput. Syst., 2011

Energy efficient many-core processor for recognition and mining using spin-based memory.

[BibT_eX]

[DOI]

Proceedings of the 2011 IEEE/ACM International Symposium on Nanoscale Architectures, 2011

IMPACT: imprecise adders for low-power approximate computing.

[BibT_eX]

[DOI]

Proceedings of the 2011 International Symposium on Low Power Electronics and Design, 2011

MDR: performance model driven runtime for heterogeneous parallel platforms.

[BibT_eX]

[DOI]

Jacques A. Pienaar

Proceedings of the 25th International Conference on Supercomputing, 2011, Tucson, AZ, USA, May 31, 2011

MACACO: Modeling and analysis of circuits for approximate computing.

[BibT_eX]

[DOI]

Amit Agarwal

Proceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design, 2011

Design of voltage-scalable meta-functions for approximate computing.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2011

VESPA: Variability emulation for System-on-Chip performance analysis.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2011

Dynamic effort scaling: managing the quality-efficiency tradeoff.

[BibT_eX]

[DOI]

Proceedings of the 48th Design Automation Conference, 2011

2010

Variation-Aware System-Level Power Analysis.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2010

Special session 11B: Hot topic hardware security: Design, test and verification issues.

[BibT_eX]

[DOI]

Swarup Bhunia

Proceedings of the 28th IEEE VLSI Test Symposium, 2010

Integrated Systems in the More-than-Moore Era: Designing Low-Cost Energy-Efficient Systems Using Heterogeneous Components.

[BibT_eX]

[DOI]

Byunghoo Jung

Proceedings of the VLSI Design 2010: 23rd International Conference on VLSI Design, 2010

Exploiting the forgiving nature of applications for scalable parallel execution.

[BibT_eX]

[DOI]

Proceedings of the 24th IEEE International Symposium on Parallel and Distributed Processing, 2010

Scalable effort hardware design: exploiting algorithmic resilience for energy efficiency.

[BibT_eX]

[DOI]

Proceedings of the 47th Design Automation Conference, 2010

Best-effort computing: re-thinking parallel software and hardware.

[BibT_eX]

[DOI]

Proceedings of the 47th Design Automation Conference, 2010

Best-effort semantic document search on GPUs.

[BibT_eX]

[DOI]

Proceedings of 3rd Workshop on General Purpose Processing on Graphics Processing Units, 2010

Secure Virtual Machine Execution under an Untrusted Management OS.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference on Cloud Computing, 2010

A Secure User Interface for Web Applications Running Under an Untrusted Operating System.

[BibT_eX]

[DOI]

Proceedings of the 10th IEEE International Conference on Computer and Information Technology, 2010

2009

Variation-Tolerant Dynamic Power Management at the System-Level.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2009

Coping with Variations through System-Level Design.

[BibT_eX]

[DOI]

Proceedings of the VLSI Design 2009: Improving Productivity through Higher Abstraction, 2009

A framework for efficient and scalable execution of domain-specific templates on GPUs.

[BibT_eX]

[DOI]

Narayanan Sundaram

Proceedings of the 23rd IEEE International Symposium on Parallel and Distributed Processing, 2009

Best-effort parallel execution framework for Recognition and mining applications.

[BibT_eX]

[DOI]

Jiayuan Meng

Proceedings of the 23rd IEEE International Symposium on Parallel and Distributed Processing, 2009

An architecture for secure software defined radio.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2009

2008

Dynamically Configurable Bus Topologies for High-Performance On-Chip Communication.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2008

Systematic Software-Based Self-Test for Pipelined Processors.

[BibT_eX]

[DOI]

Dimitris Gizopoulos

Mihalis Psarakis

Miltiadis Hatzimihail

IEEE Trans. Very Large Scale Integr. Syst., 2008

Analysis and design of a hardware/software trusted platform module for embedded systems.

[BibT_eX]

[DOI]

Najwa Aaraj

ACM Trans. Embed. Comput. Syst., 2008

Dynamic Binary Instrumentation-Based Framework for Malware Defense.

[BibT_eX]

[DOI]

Najwa Aaraj

Proceedings of the Detection of Intrusions and Malware, 2008

Efficient Software Architecture for IPSec Acceleration Using a Programmable Security Processor.

[BibT_eX]

[DOI]

Janar Thoguluva

Proceedings of the Design, Automation and Test in Europe, 2008

2007

Configuration and Extension of Embedded Processors to Optimize IPSec Protocol Execution.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2007

Aiding Side-Channel Attacks on Cryptographic Software With Satisfiability-Based Analysis.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2007

Generation of Heterogeneous Distributed Architectures for Memory-Intensive Applications Through High-Level Synthesis.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2007

Exploring Software Partitions for Fast Security Processing on a Multiprocessor Mobile SoC.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2007

Architectural Support for Run-Time Validation of Program Data Properties.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2007

Hybrid Architectures for Efficient and Secure Face Authentication in Embedded Systems.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2007

Energy-optimizing source code transformations for operating system-driven embedded software.

[BibT_eX]

[DOI]

ACM Trans. Embed. Comput. Syst., 2007

A Synthesis Methodology for Hybrid Custom Instruction and Coprocessor Generation for Extensible Processors.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007

Hybrid Simulation for Energy Estimation of Embedded Software.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007

Automated Energy/Performance Macromodeling of Embedded Software.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007

Guest Editors' Introduction: Security and Trust in Embedded-Systems Design.

[BibT_eX]

[DOI]

Patrick Schaumont

IEEE Des. Test Comput., 2007

Automatic Power Modeling of Infrastructure IP for System-on-Chip Power Analysis.

[BibT_eX]

[DOI]

Nikhil Bansal

Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007

Energy and execution time analysis of a software-based trusted platform module.

[BibT_eX]

[DOI]

Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

Accelerating System-on-Chip Power Analysis Using Hybrid Power Estimation.

[BibT_eX]

[DOI]

Mohammad Ali Ghodrat

Proceedings of the 44th Design Automation Conference, 2007

System-on-Chip Power Management Considering Leakage Power Variations.

[BibT_eX]

[DOI]

Proceedings of the 44th Design Automation Conference, 2007

2006

A Scalable Synthesis Methodology for Application-Specific Processors.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2006

The LOTTERYBUS on-chip communication architecture.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2006

Hardware-Assisted Run-Time Monitoring for Secure Program Execution on Embedded Processors.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2006

A Study of the Energy Consumption Characteristics of Cryptographic Algorithms and Security Protocols.

[BibT_eX]

[DOI]

IEEE Trans. Mob. Comput., 2006

RTL-Aware Cycle-Accurate Functional Power Estimation.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

Application-specific heterogeneous multiprocessor synthesis using extensible processors.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

Test-Volume Reduction in Systems-on-a-Chip Using Heterogeneous and Multilevel Compression Techniques.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

Use of Computation-Unit Integrated Memories in High-Level Synthesis.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

Hybrid Custom Instruction and Co-Processor Synthesis Methodology for Extensible Processors.

[BibT_eX]

[DOI]

Proceedings of the 19th International Conference on VLSI Design (VLSI Design 2006), 2006

Impact of Configurability and Extensibility on IPSec Protocol Execution on Embedded Processors.

[BibT_eX]

[DOI]

Proceedings of the 19th International Conference on VLSI Design (VLSI Design 2006), 2006

Safe Java Native Interface.

[BibT_eX]

Proceedings of the 2006 IEEE International Symposium on Secure Software Engineering, 2006

Considering process variations during system-level power analysis.

[BibT_eX]

[DOI]

Proceedings of the 2006 International Symposium on Low Power Electronics and Design, 2006

Active Learning Driven Data Acquisition for Sensor Networks.

[BibT_eX]

[DOI]

Proceedings of the 11th IEEE Symposium on Computers and Communications (ISCC 2006), 2006

Adaptive data placement in an embedded multiprocessor thread library.

[BibT_eX]

[DOI]

Phillip Stanley-Marbell

Proceedings of the Conference on Design, Automation and Test in Europe, 2006

Integrated data relocation and bus reconfiguration for adaptive system-on-chip platforms.

[BibT_eX]

[DOI]

Proceedings of the Conference on Design, Automation and Test in Europe, 2006

Satisfiability-based framework for enabling side-channel attacks on cryptographic software.

[BibT_eX]

[DOI]

Proceedings of the Conference on Design, Automation and Test in Europe: Designers' Forum, 2006

Architectures for efficient face authentication in embedded systems.

[BibT_eX]

[DOI]

Proceedings of the Conference on Design, Automation and Test in Europe: Designers' Forum, 2006

Systematic software-based self-test for pipelined processors.

[BibT_eX]

[DOI]

Mihalis Psarakis

Dimitris Gizopoulos

Miltiadis Hatzimihail

Antonis M. Paschalis

Proceedings of the 43rd Design Automation Conference, 2006

Software architecture exploration for high-performance security processing on a multiprocessor mobile SoC.

[BibT_eX]

[DOI]

Proceedings of the 43rd Design Automation Conference, 2006

Architectural support for safe software execution on embedded processors.

[BibT_eX]

[DOI]

Proceedings of the 4th International Conference on Hardware/Software Codesign and System Synthesis, 2006

2005

Energy macromodeling of embedded operating systems.

[BibT_eX]

[DOI]

ACM Trans. Embed. Comput. Syst., 2005

Input space-adaptive optimization for embedded-software synthesis.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005

Generation of distributed logic-memory architectures through high-level synthesis.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005

Synthesis of Application-Specific Heterogeneous Multiprocessor Architectures Using Extensible Processors.

[BibT_eX]

[DOI]

Proceedings of the 18th International Conference on VLSI Design (VLSI Design 2005), 2005

Heterogeneous and Multi-Level Compression Techniques for Test Volume Reduction in Systems-on-Chip.

[BibT_eX]

[DOI]

Proceedings of the 18th International Conference on VLSI Design (VLSI Design 2005), 2005

Power Monitors: A Framework for System-Level Power Estimation Using Heterogeneous Power Models.

[BibT_eX]

[DOI]

Proceedings of the 18th International Conference on VLSI Design (VLSI Design 2005), 2005

Battery discharge characteristics of wireless sensor nodes: an experimental analysis.

[BibT_eX]

[DOI]

Chulsung Park

Proceedings of the Second Annual IEEE Communications Society Conference on Sensor and Ad Hoc Communications and Networks, 2005

Hardware Accelerated Power Estimation.

[BibT_eX]

[DOI]

Joel Coburn

Proceedings of the 2005 Design, 2005

Secure Embedded Processing through Hardware-Assisted Run-Time Monitoring.

[BibT_eX]

[DOI]

Proceedings of the 2005 Design, 2005

FLEXBUS: a high-performance system-on-chip communication architecture with a dynamically configurable topology.

[BibT_eX]

[DOI]

Proceedings of the 42nd Design Automation Conference, 2005

Hybrid simulation for embedded software energy estimation.

[BibT_eX]

[DOI]

Proceedings of the 42nd Design Automation Conference, 2005

Efficient fingerprint-based user authentication for embedded systems.

[BibT_eX]

[DOI]

Proceedings of the 42nd Design Automation Conference, 2005

Power emulation: a new paradigm for power estimation.

[BibT_eX]

[DOI]

Joel Coburn

Proceedings of the 42nd Design Automation Conference, 2005

Enhancing security through hardware-assisted run-time validation of program data properties.

[BibT_eX]

[DOI]

Proceedings of the 3rd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2005

Eliminating memory bottlenecks for a JPEG encoder through distributed logic-memory architecture and computation-unit integrated memory.

[BibT_eX]

[DOI]

Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005

SECA: security-enhanced communication architecture.

[BibT_eX]

[DOI]

Proceedings of the 2005 International Conference on Compilers, 2005

2004

Input space adaptive design: a high-level methodology for optimizing energy and performance.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2004

Security in embedded systems: Design challenges.

[BibT_eX]

[DOI]

ACM Trans. Embed. Comput. Syst., 2004

Resource budgeting for Multiprocess High-level synthesis.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004

Custom-instruction synthesis for extensible-processor platforms.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004

Common-case computation: a high-level energy and performance optimization technique.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004

Design of high-performance system-on-chips using communication architecture tuners.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004

Design space exploration for optimizing on-chip communication architectures.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004

Efficient power profiling for battery-driven embedded system design.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004

A hybrid energy-estimation technique for extensible processors.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004

Profiling Driven Computation Reuse: An Embedded Software Synthesis Technique for Energy and Performance Optimization.

[BibT_eX]

[DOI]

Proceedings of the 17th International Conference on VLSI Design (VLSI Design 2004), 2004

Tamper Resistance Mechanisms for Secure, Embedded Systems.

[BibT_eX]

[DOI]

Proceedings of the 17th International Conference on VLSI Design (VLSI Design 2004), 2004

Energy-Optimizing Source Code Transformations for OS-driven Embedded Software.

[BibT_eX]

[DOI]

Proceedings of the 17th International Conference on VLSI Design (VLSI Design 2004), 2004

Power estimation for cycle-accurate functional descriptions of hardware.

[BibT_eX]

[DOI]

Proceedings of the 2004 International Conference on Computer-Aided Design, 2004

High-level synthesis using computation-unit integrated memories.

[BibT_eX]

[DOI]

Proceedings of the 2004 International Conference on Computer-Aided Design, 2004

Security as a new dimension in embedded system design.

[BibT_eX]

[DOI]

Proceedings of the 41th Design Automation Conference, 2004

An Energy-Aware Synthesis Methodology for OS-Driven Multi-Process Embedded Software.

[BibT_eX]

Proceedings of the International Conference on Embedded Systems and Applications, 2004

Power analysis of system-level on-chip communication architectures.

[BibT_eX]

[DOI]

Proceedings of the 2nd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2004

2003

High-level macro-modeling and estimation techniques for switching activity and power consumption.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2003

A simulation framework for energy-consumption analysis of OS-driven embedded applications.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003

Analysis of power dissipation in embedded systems using real-time operating systems.

[BibT_eX]

[DOI]

Robert P. Dick

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003

High-level Synthesis of Multi-process Behavioral Descriptions.

[BibT_eX]

[DOI]

Proceedings of the 16th International Conference on VLSI Design (VLSI Design 2003), 2003

Efficient RTL Power Estimation for Large Designs.

[BibT_eX]

[DOI]

Proceedings of the 16th International Conference on VLSI Design (VLSI Design 2003), 2003

Embedding Security in Wireless Embedded Systems.

[BibT_eX]

[DOI]

Proceedings of the 16th International Conference on VLSI Design (VLSI Design 2003), 2003

Analyzing the energy consumption of security protocols.

[BibT_eX]

[DOI]

Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003

A Scalable Application-Specific Processor Synthesis Methodology.

[BibT_eX]

[DOI]

Proceedings of the 2003 International Conference on Computer-Aided Design, 2003

Synthesis of Heterogeneous Distributed Architectures for Memory-Intensive Applications.

[BibT_eX]

[DOI]

Proceedings of the 2003 International Conference on Computer-Aided Design, 2003

A comprehensive high-level synthesis system for control-flow intensive behaviors.

[BibT_eX]

[DOI]

Proceedings of the 13th ACM Great Lakes Symposium on VLSI 2003, 2003

Software Architectural Transformations: A New Approach to Low Energy Embedded Software.

[BibT_eX]

[DOI]

Proceedings of the 2003 Design, 2003

Securing Mobile Appliances: New Challenges for the System Designer.

[BibT_eX]

[DOI]

Sunil Hattangady

Jean-Jacques Quisquater

Proceedings of the 2003 Design, 2003

Energy Estimation for Extensible Processors.

[BibT_eX]

[DOI]

Proceedings of the 2003 Design, 2003

Transport Protocol Optimization for Energy Efficient Wireless Embedded Systems.

[BibT_eX]

[DOI]

Proceedings of the 2003 Design, 2003

A scalable software-based self-test methodology for programmable processors.

[BibT_eX]

[DOI]

Proceedings of the 40th Design Automation Conference, 2003

Software Architectural Transformations.

[BibT_eX]

[DOI]

Proceedings of the Embedded Software for SoC, 2003

2002

Cosimulation-based power estimation for system-on-chip design.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2002

High-level energy macromodeling of embedded software.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002

Communication-Based Power Management.

[BibT_eX]

[DOI]

IEEE Des. Test Comput., 2002

Innovations in Test Automation.

[BibT_eX]

[DOI]

Proceedings of the 20th IEEE VLSI Test Symposium (VTS 2002), Without Testing It's a Gamble, 28 April, 2002

Input Space Adaptive Embedded Software Synthesis.

[BibT_eX]

[DOI]

Proceedings of the 7th Asia and South Pacific Design Automation Conference (ASP-DAC 2002), 2002

High-Level Synthesis with SIMD Units.

[BibT_eX]

[DOI]

Proceedings of the 7th Asia and South Pacific Design Automation Conference (ASP-DAC 2002), 2002

Embedded Tutorial: Battery-Driven System Design: A New Frontier in Low Power Design.

[BibT_eX]

[DOI]

Proceedings of the 7th Asia and South Pacific Design Automation Conference (ASP-DAC 2002), 2002

Securing Wireless Data: System Architecture Challenges.

[BibT_eX]

[DOI]

Proceedings of the 15th International Symposium on System Synthesis (ISSS 2002), 2002

Embedded Operating System Energy Analysis and Macro-Modeling.

[BibT_eX]

[DOI]

Proceedings of the 20th International Conference on Computer Design (ICCD 2002), 2002

Synthesis of custom processors based on extensible platforms.

[BibT_eX]

[DOI]

Proceedings of the 2002 IEEE/ACM International Conference on Computer-aided Design, 2002

High-level synthesis of distributed logic-memory architectures.

[BibT_eX]

[DOI]

Proceedings of the 2002 IEEE/ACM International Conference on Computer-aided Design, 2002

Optimizing public-key encryption for wireless clients.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference on Communications, 2002

Battery-efficient architecture for an 802.11 MAC processor.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference on Communications, 2002

System design methodologies for a wireless security processing platform.

[BibT_eX]

[DOI]

Murugan Sankaradass

Proceedings of the 39th Design Automation Conference, 2002

Communication architecture based power management for battery efficient system design.

[BibT_eX]

[DOI]

Proceedings of the 39th Design Automation Conference, 2002

Fast system-level power profiling for battery-efficient system design.

[BibT_eX]

[DOI]

Proceedings of the Tenth International Symposium on Hardware/Software Codesign, 2002

FLEXBAR: A crossbar switching fabric with improved performance and utilization.

[BibT_eX]

[DOI]

Jacob Chang

Proceedings of the IEEE 2002 Custom Integrated Circuits Conference, 2002

2001

System-level performance analysis for designing on-chipcommunication architectures.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001

Low-Power Mobile Wireless Communication System Design: Protocols, Architectures, and Design Methodologies.

[BibT_eX]

[DOI]

Proceedings of the 14th International Conference on VLSI Design (VLSI Design 2001), 2001

Accurate Power Macro-modeling Techniques for Complex RTL Circuits.

[BibT_eX]

[DOI]

Michael S. Hsiao

Carla-Fabiana Chiasserini

Proceedings of the 14th International Conference on VLSI Design (VLSI Design 2001), 2001

Battery Life Estimation of Mobile Embedded Systems.

[BibT_eX]

[DOI]

Proceedings of the 14th International Conference on VLSI Design (VLSI Design 2001), 2001

Evaluation of the Traffic-Performance Characteristics of System-on-Chip Communication Architectures.

[BibT_eX]

[DOI]

Proceedings of the 14th International Conference on VLSI Design (VLSI Design 2001), 2001

Transient Power Management Through High Level Synthesis.

[BibT_eX]

[DOI]

Proceedings of the 2001 IEEE/ACM International Conference on Computer-Aided Design, 2001

Input Space Adaptive Design: A High-level Methodology for Energy and Performance Optimization.

[BibT_eX]

[DOI]

Proceedings of the 38th Design Automation Conference, 2001

High-level Software Energy Macro-modeling.

[BibT_eX]

[DOI]

Proceedings of the 38th Design Automation Conference, 2001

LOTTERYBUS: A New High-Performance Communication Architecture for System-on-Chip Designs.

[BibT_eX]

[DOI]

Proceedings of the 38th Design Automation Conference, 2001

2000

Incorporating speculative execution into scheduling ofcontrol-flow-intensive designs.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000

Behavioral Synthesis of Fault Secure Controller/Datapaths Based on Aliasing Probability Analysis.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2000

Performance Analysis of Systems with Multi-Channel Communication Architectures.

[BibT_eX]

[DOI]

Proceedings of the 13th International Conference on VLSI Design (VLSI Design 2000), 2000

Efficient Exploration of the SoC Communication Architecture Design Space.

[BibT_eX]

[DOI]

Proceedings of the 2000 IEEE/ACM International Conference on Computer-Aided Design, 2000

Efficient Power Co-Estimation Techniques for System-on-Chip Design.

[BibT_eX]

[DOI]

Proceedings of the 2000 Design, 2000

Communication architecture tuners: a methodology for the design of high-performance communication architectures for systems-on-chips.

[BibT_eX]

[DOI]

Proceedings of the 37th Conference on Design Automation, 2000

Power analysis of embedded operating systems.

[BibT_eX]

[DOI]

Robert P. Dick

Proceedings of the 37th Conference on Design Automation, 2000

1999

Power management in high-level synthesis.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 1999

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999

Hierarchical test generation and design for testability methods for ASPPs and ASIPs.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999

Controller-based power management for control-flow intensive designs.

[BibT_eX]

[DOI]

Kazutoshi Wakabayashi

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999

Low Power Design Methodologies for Systems-on-Chips.

[BibT_eX]

[DOI]

Proceedings of the 12th International Conference on VLSI Design (VLSI Design 1999), 1999

Verification of Scheduling in the Presence of Loops Using Uninterpreted Symbolic Simulation.

[BibT_eX]

[DOI]

Pranav Ashar

Aarti Gupta

Subhrajit Bhattacharya

Proceedings of the IEEE International Conference On Computer Design, 1999

Fast performance analysis of bus-based system-on-chip communication architectures.

[BibT_eX]

[DOI]

Proceedings of the 1999 IEEE/ACM International Conference on Computer-Aided Design, 1999

Common-Case Computation: A High-Level Technique for Power and Performance Optimization.

[BibT_eX]

[DOI]

Proceedings of the 36th Conference on Design Automation, 1999

1998

A design-for-testability technique for register-transfer level circuits using control/data flow extraction.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1998

Design for Testability Techniques at the Behavioral and Register-Transfer Levels.

[BibT_eX]

[DOI]

Kenneth D. Wagner

J. Electron. Test., 1998

A Power Management Methodology for High-Level Synthesis.

[BibT_eX]

[DOI]

Proceedings of the 11th International Conference on VLSI Design (VLSI Design 1991), 1998

Transforming control-flow intensive designs to facilitate power management.

[BibT_eX]

[DOI]

Proceedings of the 1998 IEEE/ACM International Conference on Computer-Aided Design, 1998

Verification of RTL generated from scheduled behavior in a high-level synthesis flow.

[BibT_eX]

[DOI]

Pranav Ashar

Subhrajit Bhattacharya

Akira Mukaiyama

Proceedings of the 1998 IEEE/ACM International Conference on Computer-Aided Design, 1998

Incorporating Speculative Execution into Scheduling of Control-Flow Intensive Behavioral Descriptions.

[BibT_eX]

[DOI]

Alberto L. Sangiovanni-Vincentelli

Proceedings of the 35th Conference on Design Automation, 1998

A case study on modeling shared memory access effects during performance analysis of HW/SW systems.

[BibT_eX]

[DOI]

Proceedings of the Sixth International Workshop on Hardware/Software Codesign, 1998

Considering Testability during High-level Design (Embedded Tutorial).

[BibT_eX]

[DOI]

Rabindra K. Roy

Proceedings of the ASP-DAC '98, 1998

High-Level Power Analysis and Optimization.

[BibT_eX]

[DOI]

Kluwer, ISBN: 978-0-7923-8073-3, 1998

1997

SCALP: an iterative-improvement-based low-power data path synthesis system.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1997

Design for hierarchical testability of RTL circuits obtained by behavioral synthesis.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1997

Bottleneck removal algorithm for dynamic compaction in sequential circuits.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1997

Power Management Techniques for Control-Flow Intensive Designs.

[BibT_eX]

[DOI]

Kazutoshi Wakabayashi

Proceedings of the 34st Conference on Design Automation, 1997

Hierarchical Test Generation and Design for Testability of ASPPs and ASIPs.

[BibT_eX]

[DOI]

Proceedings of the 34st Conference on Design Automation, 1997

1996

Dynamic test Sequence compaction for Sequential Circuits.

[BibT_eX]

[DOI]

Proceedings of the 9th International Conference on VLSI Design (VLSI Design 1996), 1996

Controller re-specification to minimize switching activity in controller/data path circuits.

[BibT_eX]

[DOI]

Kazutoshi Wakabayashi

Proceedings of the 1996 International Symposium on Low Power Electronics and Design, 1996

[BibT_eX]

[DOI]

Proceedings of the 1996 IEEE/ACM International Conference on Computer-Aided Design, 1996

A design for testability technique for RTL circuits using control/data flow extraction.

[BibT_eX]

[DOI]

Proceedings of the 1996 IEEE/ACM International Conference on Computer-Aided Design, 1996

Behavioral Synthesis of Fault Secure Controller?Datapaths using Aliasing Probability Analysis.

[BibT_eX]

[DOI]

Proceedings of the Digest of Papers: FTCS-26, 1996

Glitch Analysis and Reduction in Register Transfer Level.

[BibT_eX]

[DOI]

Proceedings of the 33st Conference on Design Automation, 1996

1995

Test generation for cyclic combinational circuits.

[BibT_eX]

[DOI]

Pranav Ashar

Sharad Malik

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1995

An ILP Formulation for Low Power Based on Minimizing Switched Capacitance During Data Path Allocation.

[BibT_eX]

[DOI]

Proceedings of the 1995 IEEE International Symposium on Circuits and Systems, ISCAS 1995, Seattle, Washington, USA, April 30, 1995

An iterative improvement algorithm for low power data path synthesis.

[BibT_eX]

[DOI]

Proceedings of the 1995 IEEE/ACM International Conference on Computer-Aided Design, 1995

Acceleration techniques for dynamic vector compaction.

[BibT_eX]

[DOI]

Proceedings of the 1995 IEEE/ACM International Conference on Computer-Aided Design, 1995

Bottleneck removal algorithm for dynamic compaction and test cycles reduction.

[BibT_eX]

[DOI]

Proceedings of the Proceedings EURO-DAC'95, 1995

1994

Behavioral Synthesis for low Power.

[BibT_eX]

[DOI]