Kamal S. Khouri

According to our database1, Kamal S. Khouri authored at least 20 papers between 1997 and 2009.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2009
TRAM: A tool for Temperature and Reliability Aware Memory Design.
Proceedings of the Design, Automation and Test in Europe, 2009

2008
Thermal Aware Global Routing of VLSI Chips for Enhanced Reliability.
Proceedings of the 9th International Symposium on Quality of Electronic Design (ISQED 2008), 2008

2007
STEFAL: A System Level Temperature- and Floorplan-Aware Leakage Power Estimator for SoCs.
Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007

LEAF: A System Level Leakage-Aware Floorplanner for SoCs.
Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007

2006
Floorplan driven leakage power aware IP-based SoC design space exploration.
Proceedings of the 4th International Conference on Hardware/Software Codesign and System Synthesis, 2006

2005
Memory binding for performance optimization of control-flow intensive behavioral descriptions.
IEEE Trans. Very Large Scale Integr. Syst., 2005

2004
IDAP: a tool for high-level power estimation of custom array structures.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004

Common-case computation: a high-level energy and performance optimization technique.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004

Analytical models for leakage power estimation of memory array structures.
Proceedings of the 2nd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2004

2003
A Methodology for Accurate Modeling of Energy Dissipation in Array Structures.
Proceedings of the 16th International Conference on VLSI Design (VLSI Design 2003), 2003

2002
Leakage power analysis and reduction during behavioral synthesis.
IEEE Trans. Very Large Scale Integr. Syst., 2002

2001
Clock selection for performance optimization of control-flowintensive behaviors.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001

2000
Clock Selection for Performance Optimization of Control-Flow Intensive Behaviors.
Proceedings of the 13th International Conference on VLSI Design (VLSI Design 2000), 2000

1999
Wavesched: a novel scheduling technique for control-flow intensive designs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999

High-level synthesis of low-power control-flow intensive circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999

Memory binding for performance optimization of control-flow intensive behaviors.
Proceedings of the 1999 IEEE/ACM International Conference on Computer-Aided Design, 1999

Common-Case Computation: A High-Level Technique for Power and Performance Optimization.
Proceedings of the 36th Conference on Design Automation, 1999

1998
Fast high-level power estimation for control-flow intensive design.
Proceedings of the 1998 International Symposium on Low Power Electronics and Design, 1998

IMPACT: A High-Level Synthesis System for Low Power Control-Flow Intensive Circuits.
Proceedings of the 1998 Design, 1998

1997
Wavesched: a novel scheduling technique for control-flow intensive behavioral descriptions.
Proceedings of the 1997 IEEE/ACM International Conference on Computer-Aided Design, 1997


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