Srivaths Ravi

Amit Majumdar

Proceedings of the 35th IEEE VLSI Test Symposium, 2017

Demystifying automotive safety and security for semiconductor developer.

[BibT_eX]

[DOI]

V. Prasanth

David Foley

Proceedings of the IEEE International Test Conference, 2017

2015

Tutorial T2: Validation and Debug of Security and Trust Issues in Embedded Systems.

[BibT_eX]

[DOI]

Prabhat Mishra

Swarup Bhunia

Proceedings of the 28th International Conference on VLSI Design, 2015

2014

Tutorial T3A: Testing Low-Power Integrated Circuits: Challenges, Solutions, and Industry Practices.

[BibT_eX]

[DOI]

Vivek Chickermane

Krishna Chakravadhanula

Proceedings of the 2014 27th International Conference on VLSI Design, 2014

At-speed capture power reduction using layout-aware granular clock gate enable controls.

[BibT_eX]

[DOI]

Proceedings of the 2014 International Test Conference, 2014

Methodology for Early RTL Testability and Coverage Analysis and Its Application to Industrial Designs.

[BibT_eX]

[DOI]

Proceedings of the 23rd IEEE Asian Test Symposium, 2014

2011

Design Techniques with Multiple Scan Compression CoDecs for Low Power and High Quality Scan Test.

[BibT_eX]

[DOI]

Arvind Jain

Sundarrajan Subramanian

J. Low Power Electron., 2011

Multi-CoDec Configurations for Low Power and High Quality Scan Test.

[BibT_eX]

[DOI]

Arvind Jain

Sundarrajan Subramanian

Proceedings of the VLSI Design 2011: 24th International Conference on VLSI Design, 2011

2010

A generic low power scan chain wrapper for designs using scan compression.

[BibT_eX]

[DOI]

Proceedings of the 28th IEEE VLSI Test Symposium, 2010

Methodology for early and accurate test power estimation at RTL.

[BibT_eX]

[DOI]

Proceedings of the 2011 IEEE International Test Conference, 2010

2009

Test Power Reduction Using Integrated Scan Cell and Test Vector Reordering Techniques on Linear Scan and Double Tree Scan Architectures.

[BibT_eX]

[DOI]

J. Low Power Electron., 2009

2008

Systematic Software-Based Self-Test for Pipelined Processors.

[BibT_eX]

[DOI]

Dimitris Gizopoulos

Mihalis Psarakis

Miltiadis Hatzimihail

IEEE Trans. Very Large Scale Integr. Syst., 2008

Low Power Test for Nanometer System-on-Chips (SoCs).

[BibT_eX]

[DOI]

Jayashree Saxena

J. Low Power Electron., 2008

A Regression Based Technique for ATE-Aware Test Data Volume Estimation of System-on-Chips.

[BibT_eX]

[DOI]

Proceedings of the 26th IEEE VLSI Test Symposium (VTS 2008), April 27, 2008

Variability-Tolerant Register-Transfer Level Synthesis.

[BibT_eX]

[DOI]

Anish Muttreja

Proceedings of the 21st International Conference on VLSI Design (VLSI Design 2008), 2008

Power Analysis and Reduction Techniques for Transition Fault Testing.

[BibT_eX]

[DOI]

Proceedings of the 17th IEEE Asian Test Symposium, 2008

2007

Configuration and Extension of Embedded Processors to Optimize IPSec Protocol Execution.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2007

Aiding Side-Channel Attacks on Cryptographic Software With Satisfiability-Based Analysis.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2007

Generation of Heterogeneous Distributed Architectures for Memory-Intensive Applications Through High-Level Synthesis.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2007

Exploring Software Partitions for Fast Security Processing on a Multiprocessor Mobile SoC.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2007

Architectural Support for Run-Time Validation of Program Data Properties.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2007

Hybrid Architectures for Efficient and Secure Face Authentication in Embedded Systems.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2007

Energy-optimizing source code transformations for operating system-driven embedded software.

[BibT_eX]

[DOI]

ACM Trans. Embed. Comput. Syst., 2007

A Synthesis Methodology for Hybrid Custom Instruction and Coprocessor Generation for Extensible Processors.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007

Hybrid Simulation for Energy Estimation of Embedded Software.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007

Automated Energy/Performance Macromodeling of Embedded Software.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007

Tutorial T1: Designing Secure SoCs.

[BibT_eX]

[DOI]

Stefan Mangard

Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007

Power-aware test: Challenges and solutions.

[BibT_eX]

[DOI]

Proceedings of the 2007 IEEE International Test Conference, 2007

Methodology for low power test pattern generation using activity threshold control logic.

[BibT_eX]

[DOI]

V. R. Devanathan

Proceedings of the 2007 International Conference on Computer-Aided Design, 2007

Energy and execution time analysis of a software-based trusted platform module.

[BibT_eX]

[DOI]

Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

2006

A Scalable Synthesis Methodology for Application-Specific Processors.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2006

Hardware-Assisted Run-Time Monitoring for Secure Program Execution on Embedded Processors.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2006

A Study of the Energy Consumption Characteristics of Cryptographic Algorithms and Security Protocols.

[BibT_eX]

[DOI]

IEEE Trans. Mob. Comput., 2006

RTL-Aware Cycle-Accurate Functional Power Estimation.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

Application-specific heterogeneous multiprocessor synthesis using extensible processors.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

Test-Volume Reduction in Systems-on-a-Chip Using Heterogeneous and Multilevel Compression Techniques.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

Satisfiability-based test generation for nonseparable RTL controller-datapath circuits.

[BibT_eX]

[DOI]

Loganathan Lingappan

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

Use of Computation-Unit Integrated Memories in High-Level Synthesis.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

Hybrid Custom Instruction and Co-Processor Synthesis Methodology for Extensible Processors.

[BibT_eX]

[DOI]

Proceedings of the 19th International Conference on VLSI Design (VLSI Design 2006), 2006

Impact of Configurability and Extensibility on IPSec Protocol Execution on Embedded Processors.

[BibT_eX]

[DOI]

Proceedings of the 19th International Conference on VLSI Design (VLSI Design 2006), 2006

Safe Java Native Interface.

[BibT_eX]

Proceedings of the 2006 IEEE International Symposium on Secure Software Engineering, 2006

Active Learning Driven Data Acquisition for Sensor Networks.

[BibT_eX]

[DOI]

Proceedings of the 11th IEEE Symposium on Computers and Communications (ISCC 2006), 2006

Satisfiability-based framework for enabling side-channel attacks on cryptographic software.

[BibT_eX]

[DOI]

Proceedings of the Conference on Design, Automation and Test in Europe: Designers' Forum, 2006

Architectures for efficient face authentication in embedded systems.

[BibT_eX]

[DOI]

Proceedings of the Conference on Design, Automation and Test in Europe: Designers' Forum, 2006

Systematic software-based self-test for pipelined processors.

[BibT_eX]

[DOI]

Mihalis Psarakis

Dimitris Gizopoulos

Miltiadis Hatzimihail

Antonis M. Paschalis

Proceedings of the 43rd Design Automation Conference, 2006

Software architecture exploration for high-performance security processing on a multiprocessor mobile SoC.

[BibT_eX]

[DOI]

Proceedings of the 43rd Design Automation Conference, 2006

Architectural support for safe software execution on embedded processors.

[BibT_eX]

[DOI]

Proceedings of the 4th International Conference on Hardware/Software Codesign and System Synthesis, 2006

2005

Generation of distributed logic-memory architectures through high-level synthesis.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005

Synthesis of Application-Specific Heterogeneous Multiprocessor Architectures Using Extensible Processors.

[BibT_eX]

[DOI]

Proceedings of the 18th International Conference on VLSI Design (VLSI Design 2005), 2005

Heterogeneous and Multi-Level Compression Techniques for Test Volume Reduction in Systems-on-Chip.

[BibT_eX]

[DOI]

Proceedings of the 18th International Conference on VLSI Design (VLSI Design 2005), 2005

Hardware Accelerated Power Estimation.

[BibT_eX]

[DOI]

Joel Coburn

Proceedings of the 2005 Design, 2005

Secure Embedded Processing through Hardware-Assisted Run-Time Monitoring.

[BibT_eX]

[DOI]

Proceedings of the 2005 Design, 2005

Hybrid simulation for embedded software energy estimation.

[BibT_eX]

[DOI]

Proceedings of the 42nd Design Automation Conference, 2005

Efficient fingerprint-based user authentication for embedded systems.

[BibT_eX]

[DOI]

Proceedings of the 42nd Design Automation Conference, 2005

Power emulation: a new paradigm for power estimation.

[BibT_eX]

[DOI]

Joel Coburn

Proceedings of the 42nd Design Automation Conference, 2005

Enhancing security through hardware-assisted run-time validation of program data properties.

[BibT_eX]

[DOI]

Proceedings of the 3rd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2005

Eliminating memory bottlenecks for a JPEG encoder through distributed logic-memory architecture and computation-unit integrated memory.

[BibT_eX]

[DOI]

Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005

SECA: security-enhanced communication architecture.

[BibT_eX]

[DOI]

Proceedings of the 2005 International Conference on Compilers, 2005

2004

Security in embedded systems: Design challenges.

[BibT_eX]

[DOI]

ACM Trans. Embed. Comput. Syst., 2004

Custom-instruction synthesis for extensible-processor platforms.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004

A hybrid energy-estimation technique for extensible processors.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004

Tamper Resistance Mechanisms for Secure, Embedded Systems.

[BibT_eX]

[DOI]

Srimat T. Chakradhar

Proceedings of the 17th International Conference on VLSI Design (VLSI Design 2004), 2004

Energy-Optimizing Source Code Transformations for OS-driven Embedded Software.

[BibT_eX]

[DOI]

Proceedings of the 17th International Conference on VLSI Design (VLSI Design 2004), 2004

Power estimation for cycle-accurate functional descriptions of hardware.

[BibT_eX]

[DOI]

Proceedings of the 2004 International Conference on Computer-Aided Design, 2004

High-level synthesis using computation-unit integrated memories.

[BibT_eX]

[DOI]

Proceedings of the 2004 International Conference on Computer-Aided Design, 2004

Security as a new dimension in embedded system design.

[BibT_eX]

[DOI]

Proceedings of the 41th Design Automation Conference, 2004

2003

Efficient RTL Power Estimation for Large Designs.

[BibT_eX]

[DOI]

Srimat T. Chakradhar

Proceedings of the 16th International Conference on VLSI Design (VLSI Design 2003), 2003

Embedding Security in Wireless Embedded Systems.

[BibT_eX]

[DOI]

Srimat T. Chakradhar

Proceedings of the 16th International Conference on VLSI Design (VLSI Design 2003), 2003

Analyzing the energy consumption of security protocols.

[BibT_eX]

[DOI]

Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003

Test Generation for Non-separable RTL Controller-datapath Circuits using a Satisfiability based Approach.

[BibT_eX]

[DOI]

Loganathan Lingappan

Proceedings of the 21st International Conference on Computer Design (ICCD 2003), 2003

A Scalable Application-Specific Processor Synthesis Methodology.

[BibT_eX]

[DOI]

Proceedings of the 2003 International Conference on Computer-Aided Design, 2003

Synthesis of Heterogeneous Distributed Architectures for Memory-Intensive Applications.

[BibT_eX]

[DOI]

Proceedings of the 2003 International Conference on Computer-Aided Design, 2003

On automatic generation of RTL validation test benches using circuit testing techniques.

[BibT_eX]

[DOI]

Indradeep Ghosh

Proceedings of the 13th ACM Great Lakes Symposium on VLSI 2003, 2003

Securing Mobile Appliances: New Challenges for the System Designer.

[BibT_eX]

[DOI]

Sunil Hattangady

Jean-Jacques Quisquater

Proceedings of the 2003 Design, 2003

Energy Estimation for Extensible Processors.

[BibT_eX]

[DOI]

Proceedings of the 2003 Design, 2003

Transport Protocol Optimization for Energy Efficient Wireless Embedded Systems.

[BibT_eX]

[DOI]

Proceedings of the 2003 Design, 2003

A scalable software-based self-test methodology for programmable processors.

[BibT_eX]

[DOI]

Proceedings of the 40th Design Automation Conference, 2003

2002

High-level test compaction techniques.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002

Test synthesis of systems-on-a-chip.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002

Special Session: Security on SoC.

[BibT_eX]

[DOI]

Proceedings of the 15th International Symposium on System Synthesis (ISSS 2002), 2002

Securing Wireless Data: System Architecture Challenges.

[BibT_eX]

[DOI]

Proceedings of the 15th International Symposium on System Synthesis (ISSS 2002), 2002

Synthesis of custom processors based on extensible platforms.

[BibT_eX]

[DOI]

Proceedings of the 2002 IEEE/ACM International Conference on Computer-aided Design, 2002

High-level synthesis of distributed logic-memory architectures.

[BibT_eX]

[DOI]

Proceedings of the 2002 IEEE/ACM International Conference on Computer-aided Design, 2002

Optimizing public-key encryption for wireless clients.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference on Communications, 2002

System design methodologies for a wireless security processing platform.

[BibT_eX]

[DOI]

Murugan Sankaradass

Proceedings of the 39th Design Automation Conference, 2002

FLEXBAR: A crossbar switching fabric with improved performance and utilization.

[BibT_eX]

[DOI]

Jacob Chang

Proceedings of the IEEE 2002 Custom Integrated Circuits Conference, 2002

2001

TAO: regular expression-based register-transfer level testability analysis and optimization.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2001

Testing of core-based systems-on-a-chip.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001

Fault-diagnosis-based technique for establishing RTL and gate-levelcorrespondences.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001

Synthesis of System-on-a-chip for Testability.

[BibT_eX]

[DOI]

Proceedings of the 14th International Conference on VLSI Design (VLSI Design 2001), 2001

Fast test generation for circuits with RTL and gate-level views.

[BibT_eX]

[DOI]

Proceedings of the Proceedings IEEE International Test Conference 2001, Baltimore, MD, USA, 30 October, 2001

Transient Power Management Through High Level Synthesis.

[BibT_eX]

[DOI]

Vijay Raghunathan

Proceedings of the 2001 IEEE/ACM International Conference on Computer-Aided Design, 2001

2000

TAO-BIST: A framework for testability analysis and optimization forbuilt-in self-test of RTL circuits.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000

Integrating variable-latency components into high-level synthesis.

[BibT_eX]

[DOI]

Vijay Raghunathan

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000

High-Level Synthesis with Variable-Latency Components.

[BibT_eX]

[DOI]

Vijay Raghunathan

Proceedings of the 13th International Conference on VLSI Design (VLSI Design 2000), 2000

: Reducing test application time in high-level test generation.

[BibT_eX]

[DOI]

Proceedings of the Proceedings IEEE International Test Conference 2000, 2000

A Technique for Identifying RTL and Gate-Level Correspondences.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference On Computer Design: VLSI In Computers & Processors, 2000

1999

TAO-BIST: A Framework for Testability Analysis and Optimizationb of RTL Circuits for BIST.

[BibT_eX]

[DOI]

Proceedings of the 17th IEEE VLSI Test Symposium (VTS '99), 1999

A framework for testing core-based systems-on-a-chip.

[BibT_eX]

[DOI]

Proceedings of the 1999 IEEE/ACM International Conference on Computer-Aided Design, 1999

1998

Controller Resynthesis for Testability Enhancement of RTL Controller/Data Path Circuits.

[BibT_eX]

[DOI]

J. Electron. Test., 1998

TAO: regular expression based high-level testability analysis and optimization.

[BibT_eX]

[DOI]

Proceedings of the Proceedings IEEE International Test Conference 1998, 1998

Removal of memory access bottlenecks for scheduling control-flow intensive behavioral descriptions.

[BibT_eX]

[DOI]