Gerald G. Pechanek

According to our database1, Gerald G. Pechanek authored at least 20 papers between 1991 and 2017.

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Bibliography

2017
An introduction to an array memory processor for application specific acceleration.
Proceedings of the 2017 IEEE High Performance Extreme Computing Conference, 2017

2003
Indirect VLIW memory allocation for the ManArray multiprocessor DSP.
SIGARCH Computer Architecture News, 2003

2001
On Chaos and Neural Networks: The Backpropagation Paradigm.
Artif. Intell. Rev., 2001

2000
A look inside the learning process of neural networks.
Complexity, 2000

A 90k Gate "CLB" for Parallel Distributed Computing.
Proceedings of the Parallel and Distributed Processing, 2000

The ManArray( Embedded Processor Architecture.
Proceedings of the 26th EUROMICRO 2000 Conference, 2000

1999
A neuro-emulator with embedded capabilities for generalized learning.
Journal of Systems Architecture, 1999

ManArray Processor Interconnection Network: An Introduction.
Proceedings of the Euro-Par '99 Parallel Processing, 5th International Euro-Par Conference, Toulouse, France, August 31, 1999

1998
Chaos and Neural Network Learning. Some Observations.
Neural Processing Letters, 1998

The Sum-Absolute-Difference Motion Estimation Accelerato.
Proceedings of the 24th EUROMICRO '98 Conference, 1998

1996
A neuro-emulator with learning and virtual emulation capabilities.
Proceedings of International Conference on Neural Networks (ICNN'96), 1996

Architectural simulation system for M.f.a.s.t.
Proceedings of the Proceedings 29st Annual Simulation Symposium (SS '96), 1996

1995
A Neuro-Architecture with Embedded Learning.
Proceedings of the Seventh IASTED/ISMM International Conference on Parallel and Distributed Computing and Systems, 1995

MFAST: a single chip highly parallel image processing architecture.
Proceedings of the Proceedings 1995 International Conference on Image Processing, 1995

XOR and backpropagation learning: in and out of the chaos?
Proceedings of the ESANN 1995, 1995

1993
Spin: the Sequential Pipelined Neuroemulator.
International Journal on Artificial Intelligence Tools, 1993

A massively parallel diagonal-fold array processor.
Proceedings of the International Conference on Application-Specific Array Processors, 1993

1992
Digital neural emulators using tree accumulation and communication structures.
IEEE Trans. Neural Networks, 1992

1991
SPIN: a sequential pipelined neurocomputer.
Proceedings of the Third International Conference on Tools for Artificial Intelligence, 1991



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