Koen Bertels

According to our database1, Koen Bertels authored at least 206 papers between 1992 and 2021.

Collaborative distances:
  • Dijkstra number2 of three.
  • Erdős number3 of two.

Timeline

Legend:

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PhD thesis 
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Online presence:

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Bibliography

2021
Efficient decomposition of unitary matrices in quantum circuit compilers.
CoRR, 2021

2020
Skeleton-Based Synthesis Flow for Computation-in-Memory Architectures.
IEEE Trans. Emerg. Top. Comput., 2020

Comparing Neural Network Based Decoders for the Surface Code.
IEEE Trans. Computers, 2020

Decoding surface code with a distributed neural network-based decoder.
Quantum Mach. Intell., 2020

ACSS-q: Algorithmic complexity for short strings via quantum accelerated approach.
CoRR, 2020

Quantum Accelerated Estimation of Algorithmic Information.
CoRR, 2020

OpenQL : A Portable Quantum Programming Framework for Quantum Accelerators.
CoRR, 2020

QuASeR - Quantum Accelerated De Novo DNA Sequence Reconstruction.
CoRR, 2020

Evaluation of Parameterized Quantum Circuits: on the design, and the relation between classification accuracy, expressibility and entangling capability.
CoRR, 2020

GPU acceleration of Darwin read overlapper for de novo assembly of long DNA reads.
BMC Bioinform., 2020

Integration and Evaluation of Quantum Accelerators for Data-Driven User Functions.
Proceedings of the 21st International Symposium on Quality Electronic Design, 2020

Quantum Computer Architecture: Towards Full-Stack Quantum Accelerators.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

2019
A control microarchitecture for fault-tolerant quantum computing.
Microprocess. Microsystems, 2019

Correction to: GASAL2: a GPU accelerated sequence alignment library for high-throughput NGS data.
BMC Bioinform., 2019

GASAL2: a GPU accelerated sequence alignment library for high-throughput NGS data.
BMC Bioinform., 2019

Quantum Accelerated Computer Architectures.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

eQASM: An Executable Quantum Instruction Set Architecture.
Proceedings of the 25th IEEE International Symposium on High Performance Computer Architecture, 2019

Rebooting Our Computing Models.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

2018
A Mapping Methodology of Boolean Logic Circuits on Memristor Crossbar.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

Memory and Communication Profiling for Accelerator-Based Platforms.
IEEE Trans. Computers, 2018

A Microarchitecture for a Superconducting Quantum Processor.
IEEE Micro, 2018

Hardware acceleration of BWA-MEM genomic short read mapping for longer read lengths.
Comput. Biol. Chem., 2018

Towards a scalable quantum computer.
Proceedings of the 13th International Conference on Design & Technology of Integrated Systems In Nanoscale Era, 2018

Theoretical and practical aspects of verification of quantum computers.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

An Efficient GPU-Based de Bruijn Graph Construction Algorithm for Micro-Assembly.
Proceedings of the 18th IEEE International Conference on Bioinformatics and Bioengineering, 2018

Comparative Analysis of System-Level Acceleration Techniques in Bioinformatics: A Case Study of Accelerating the Smith-Waterman Algorithm for BWA-MEM.
Proceedings of the 18th IEEE International Conference on Bioinformatics and Bioengineering, 2018

2017
On the Implementation of Computation-in-Memory Parallel Adder.
IEEE Trans. Very Large Scale Integr. Syst., 2017

The First 25 Years of the FPL Conference: Significant Papers.
ACM Trans. Reconfigurable Technol. Syst., 2017

An Architecture for Integrated Near-Data Processors.
ACM Trans. Archit. Code Optim., 2017

An Experimental Microarchitecture for a Superconducting Quantum Processor.
CoRR, 2017

An experimental microarchitecture for a superconducting quantum processor.
Proceedings of the 50th Annual IEEE/ACM International Symposium on Microarchitecture, 2017

Tight Bounds in Message Delays Despite Faults in a Class of Line Digraph Networks.
Proceedings of the 14th International Symposium on Pervasive Systems, 2017

Boosting the Efficiency of HPCG and Graph500 with Near-Data Processing.
Proceedings of the 46th International Conference on Parallel Processing, 2017

Region based containers - A new paradigm for the analysis of fault tolerant networks.
Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2017

QX: A high-performance quantum computer simulation platform.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

Memristor for computing: Myth or reality?
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

The engineering challenges in quantum computing.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

Pauli Frames for Quantum Computer Architectures.
Proceedings of the 54th Annual Design Automation Conference, 2017

Sorting big data on heterogeneous near-data processing systems.
Proceedings of the Computing Frontiers Conference, 2017

GPU accelerated API for alignment of genomics sequencing data.
Proceedings of the 2017 IEEE International Conference on Bioinformatics and Biomedicine, 2017

GPU-Accelerated GATK HaplotypeCaller with Load-Balanced Multi-Process Optimization.
Proceedings of the 17th IEEE International Conference on Bioinformatics and Bioengineering, 2017

Predictive Genome Analysis Using Partial DNA Sequencing Data.
Proceedings of the 17th IEEE International Conference on Bioinformatics and Bioengineering, 2017

2016
A Survey and Evaluation of FPGA High-Level Synthesis Tools.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016

An Efficient GPUAccelerated Implementation of Genomic Short Read Mapping with BWAMEM.
SIGARCH Comput. Archit. News, 2016

An Image Processing VLIW Architecture for Real-Time Depth Detection.
Proceedings of the 28th International Symposium on Computer Architecture and High Performance Computing, 2016

Power-efficiency analysis of accelerated BWA-MEM implementations on heterogeneous computing platforms.
Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2016

Skeleton-based design and simulation flow for Computation-in-Memory architectures.
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2016

Synthesizing HDL to memristor technology: A generic framework.
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2016

Parallel matrix multiplication on memristor-based computation-in-memory architecture.
Proceedings of the International Conference on High Performance Computing & Simulation, 2016

Non-volatile look-up table based FPGA implementations.
Proceedings of the 11th International Design & Test Symposium, 2016

Power-Efficient Accelerated Genomic Short Read Mapping on Heterogeneous Computing Platforms.
Proceedings of the 24th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2016

Boolean logic gate exploration for memristor crossbar.
Proceedings of the 2016 International Conference on Design and Technology of Integrated Systems in Nanoscale Era, 2016

An architecture for near-data processing systems.
Proceedings of the ACM International Conference on Computing Frontiers, CF'16, 2016

CryoCMOS hardware technology a classical infrastructure for a scalable quantum computer.
Proceedings of the ACM International Conference on Computing Frontiers, CF'16, 2016

A heterogeneous quantum computer architecture.
Proceedings of the ACM International Conference on Computing Frontiers, CF'16, 2016

Exploration of alternative GPU implementations of the pair-HMMs forward algorithm.
Proceedings of the IEEE International Conference on Bioinformatics and Biomedicine, 2016

A comparison of seed-and-extend techniques in modern DNA read alignment algorithms.
Proceedings of the IEEE International Conference on Bioinformatics and Biomedicine, 2016

Balancing High-Performance Parallelization and Accuracy in Canny Edge Detector.
Proceedings of the Architecture of Computing Systems - ARCS 2016, 2016

GPU-Accelerated BWA-MEM Genomic Mapping Algorithm Using Adaptive Load Balancing.
Proceedings of the Architecture of Computing Systems - ARCS 2016, 2016

2015
Guest Editorial ARC 2014.
ACM Trans. Reconfigurable Technol. Syst., 2015

Challenges in exascale radio astronomy: Can the SKA ride the technology wave?
Int. J. High Perform. Comput. Appl., 2015

An FPGA-based systolic array to accelerate the BWA-MEM genomic mapping algorithm.
Proceedings of the 2015 International Conference on Embedded Computer Systems: Architectures, 2015

Calculation of worst-case execution time for multicore processors using deterministic execution.
Proceedings of the 25th International Workshop on Power and Timing Modeling, 2015

Interconnect networks for memristor crossbar.
Proceedings of the 2015 IEEE/ACM International Symposium on Nanoscale Architectures, 2015

Computation-in-memory based parallel adder.
Proceedings of the 2015 IEEE/ACM International Symposium on Nanoscale Architectures, 2015

Communication-Aware Parallelization Strategies for High Performance Applications.
Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015

Quantum computing: How far away is it?
Proceedings of the 2015 International Conference on High Performance Computing & Simulation, 2015

Memory profiling for intra-application data-communication quantification: A survey.
Proceedings of the 10th International Design & Test Symposium, 2015

Fast boolean logic mapped on memristor crossbar.
Proceedings of the 33rd IEEE International Conference on Computer Design, 2015

Heterogeneous Hardware/Software Acceleration of the BWA-MEM DNA Alignment Algorithm.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2015

Significant papers from the first 25 years of the FPL conference.
Proceedings of the 25th International Conference on Field Programmable Logic and Applications, 2015

Memristor based computation-in-memory architecture for data-intensive applications.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

Heterogeneous Hardware Accelerators with Hybrid Interconnect: An Automated Design Approach.
Proceedings of the 2015 International Conference on Advanced Computing and Applications, 2015

2014
Efficent and highly portable deterministic multithreading (DetLock).
Computing, 2014

Exascale Radio Astronomy: Can We Ride the Technology Wave?
Proceedings of the Supercomputing - 29th International Conference, 2014

Automated Hybrid Interconnect Design for FPGA Accelerators Using Data Communication Profiling.
Proceedings of the 2014 IEEE International Parallel & Distributed Processing Symposium Workshops, 2014

FPGA-accelerated Monte-Carlo integration using stratified sampling and Brownian bridges.
Proceedings of the 2014 International Conference on Field-Programmable Technology, 2014

Co-processing with dynamic reconfiguration on heterogeneous MPSoC: practices and design tradeoffs (abstract only).
Proceedings of the 2014 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2014

High-Level Synthesis in the Delft Workbench Hardware/Software Co-design Tool-Chain.
Proceedings of the 12th IEEE International Conference on Embedded and Ubiquitous Computing, 2014

Region Disjoint Paths in a Class of Optimal Line Graph Networks.
Proceedings of the 17th IEEE International Conference on Computational Science and Engineering, 2014

DRuiD: Designing reconfigurable architectures with decision-making support.
Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014

2013
Quipu: A Statistical Model for Predicting Hardware Resources.
ACM Trans. Reconfigurable Technol. Syst., 2013

Controlling a complete hardware synthesis toolchain with LARA aspects.
Microprocess. Microsystems, 2013

Fault tolerance on multicore processors using deterministic multithreading.
Proceedings of the 8th International Design and Test Symposium, 2013

Accurate and efficient identification of worst-case execution time for multicore processors: A survey.
Proceedings of the 8th International Design and Test Symposium, 2013

Run-time optimization of a dynamically reconfigurable embedded system through performance prediction.
Proceedings of the 23rd International Conference on Field programmable Logic and Applications, 2013

Evaluation Methodology for Data Communication-Aware Application Partitioning.
Proceedings of the Euro-Par 2013: Parallel Processing Workshops, 2013

Hybrid interconnect design for heterogeneous hardware accelerators.
Proceedings of the Design, Automation and Test in Europe, 2013

Efficient software-based fault tolerance approach on multicore platforms.
Proceedings of the Design, Automation and Test in Europe, 2013

Nature Inspired Self Organization for Adhoc Grids.
Proceedings of the 27th IEEE International Conference on Advanced Information Networking and Applications, 2013

Heterogeneous hardware accelerators interconnect: An overview.
Proceedings of the 2013 NASA/ESA Conference on Adaptive Hardware and Systems, 2013

2012
Parallel implementation of Gray Level Co-occurrence Matrices and Haralick texture features on cell architecture.
J. Supercomput., 2012

Evaluation of Runtime Task Mapping Using the rSesame Framework.
Int. J. Reconfigurable Comput., 2012

Self-Adaptive Economic-Based Resource Allocation in Ad-Hoc Grids.
Int. J. Embed. Real Time Commun. Syst., 2012

DetLock: Portable and Efficient Deterministic Execution for Shared Memory Multicore Systems.
Proceedings of the 2012 SC Companion: High Performance Computing, 2012

A heuristic-based communication-aware hardware optimization approach in heterogeneous multicore systems.
Proceedings of the 2012 International Conference on Reconfigurable Computing and FPGAs, 2012

A lightweight speculative and predicative scheme for hardware execution.
Proceedings of the 2012 International Conference on Reconfigurable Computing and FPGAs, 2012

Communication-aware HW/SW co-design for heterogeneous multicore platforms.
Proceedings of the International Workshop on Dynamic Analysis: held in conjunction with the ACM SIGSOFT International Symposium on Software Testing and Analysis (ISSTA 2012), 2012

Task Scheduling in Large-scale Distributed Systems Utilizing Partial Reconfigurable Processing Elements.
Proceedings of the 26th IEEE International Parallel and Distributed Processing Symposium Workshops & PhD Forum, 2012

Rule-based data communication optimization using quantitative communication profiling.
Proceedings of the 2012 International Conference on Field-Programmable Technology, 2012

Area constraint propagation in high level synthesis.
Proceedings of the 2012 International Conference on Field-Programmable Technology, 2012

DWARV 2.0: A CoSy-based C-to-VHDL hardware compiler.
Proceedings of the 22nd International Conference on Field Programmable Logic and Applications (FPL), 2012

A user-level library for fault tolerance on shared memory multicore systems.
Proceedings of the IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2012

Using multi-objective design space exploration to enable run-time resource management for reconfigurable architectures.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

EU Collaborative Research on Application-Specific Systems.
Proceedings of the 23rd IEEE International Conference on Application-Specific Systems, 2012

The Q2 Profiling Framework: Driving Application Mapping for Heterogeneous Reconfigurable Platforms.
Proceedings of the Reconfigurable Computing: Architectures, Tools and Applications, 2012

2011
The Instruction-Set Extension Problem: A Survey.
ACM Trans. Reconfigurable Technol. Syst., 2011

High level quantitative hardware prediction modeling using statistical methods.
Proceedings of the 2011 International Conference on Embedded Computer Systems: Architectures, 2011

Runtime extraction of memory access information from the application source code.
Proceedings of the 2011 International Conference on High Performance Computing & Simulation, 2011

Task scheduling strategies for dynamic reconfigurable processors in distributed systems.
Proceedings of the 2011 International Conference on High Performance Computing & Simulation, 2011

Survey of fault tolerance techniques for shared memory multicore/multiprocessor systems.
Proceedings of the 6th IEEE International Design and Test Workshop, 2011

A Simulation Framework for Reconfigurable Processors in Large-Scale Distributed Systems.
Proceedings of the 2011 International Conference on Parallel Processing Workshops, 2011

SMECY: smart multi-core embedded systems.
Proceedings of the 21st ACM Great Lakes Symposium on VLSI 2010, 2011

Loop distribution for K-loops on Reconfigurable Architectures.
Proceedings of the Design, Automation and Test in Europe, 2011

IP-XACT extensions for Reconfigurable Computing.
Proceedings of the 22nd IEEE International Conference on Application-specific Systems, 2011

2010
Runtime multitasking support on polymorphic platforms.
SIGARCH Comput. Archit. News, 2010

HArtes: Hardware-Software Codesign for Heterogeneous Multicore Platforms.
IEEE Micro, 2010

Efficient task scheduling for runtime reconfigurable systems.
J. Syst. Archit., 2010

A novel configuration circuit architecture to speedup reconfiguration and relocation for partially reconfigurable devices.
Proceedings of the IEEE 8th Symposium on Application Specific Processors, 2010

Runtime Task Mapping Based on Hardware Configuration Reuse.
Proceedings of the ReConFig'10: 2010 International Conference on Reconfigurable Computing and FPGAs, 2010

A Runtime Profiler: Toward Virtualization of Polymorphic Computing Platforms.
Proceedings of the ReConFig'10: 2010 International Conference on Reconfigurable Computing and FPGAs, 2010

Interfacing Operating Systems and Polymorphic Computing Platforms Based on the MOLEN Programming Paradigm.
Proceedings of the Computer Architecture, 2010

Fast Smith-Waterman hardware implementation.
Proceedings of the 24th IEEE International Symposium on Parallel and Distributed Processing, 2010

Performance and bandwidth optimization for biological sequence alignment.
Proceedings of the 5th International Design and Test Workshop, 2010

tQUAD - Memory Bandwidth Usage Analysis.
Proceedings of the 39th International Conference on Parallel Processing, 2010

A parallel FPGA design of the Smith-Waterman traceback.
Proceedings of the International Conference on Field-Programmable Technology, 2010

A novel HDL coding style to reduce power consumption for reconfigurable devices.
Proceedings of the International Conference on Field-Programmable Technology, 2010

Efficient hardware task reuse and interrupt handling mechanisms for FPGA-based partially reconfigurable systems.
Proceedings of the International Conference on Field-Programmable Technology, 2010

A Communication Aware Online Task Scheduling Algorithm for FPGA-Based Partially Reconfigurable Systems.
Proceedings of the 18th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2010

Evaluation of runtime task mapping heuristics with rSesame - a case study.
Proceedings of the Design, Automation and Test in Europe, 2010

Effect of the Degree of Neighborhood on Resource Discovery in Ad Hoc Grids.
Proceedings of the Architecture of Computing Systems, 2010

QUAD - A Memory Access Pattern Analyser.
Proceedings of the Reconfigurable Computing: Architectures, 2010

3D Compaction: A Novel Blocking-Aware Algorithm for Online Hardware Task Scheduling and Placement on 2D Partially Reconfigurable Devices.
Proceedings of the Reconfigurable Computing: Architectures, 2010

2009
Optimal Loop Unrolling and Shifting for Reconfigurable Architectures.
ACM Trans. Reconfigurable Technol. Syst., 2009

Runtime Memory Allocation in a Heterogeneous Reconfigurable Platform.
Proceedings of the ReConFig'09: 2009 International Conference on Reconfigurable Computing and FPGAs, 2009

A New Approach to Implement Discrete Wavelet Transform Using Collaboration of Reconfigurable Elements.
Proceedings of the ReConFig'09: 2009 International Conference on Reconfigurable Computing and FPGAs, 2009

hArtes design flow for heterogeneous platforms.
Proceedings of the 10th International Symposium on Quality of Electronic Design (ISQED 2009), 2009

Runtime decision of hardware or software execution on a heterogeneous reconfigurable platform.
Proceedings of the 23rd IEEE International Symposium on Parallel and Distributed Processing, 2009

System-level runtime mapping exploration of reconfigurable architectures.
Proceedings of the 23rd IEEE International Symposium on Parallel and Distributed Processing, 2009

Flexible pipelining design for recursive variable expansion.
Proceedings of the 23rd IEEE International Symposium on Parallel and Distributed Processing, 2009

Resource Discovery with Dynamic Matchmakers in Ad Hoc Grid.
Proceedings of the Fourth International Conference on Systems, 2009

Ant Colony Inspired Microeconomic Based Resource Management in Ad Hoc Grids.
Proceedings of the Advances in Grid and Pervasive Computing, 4th International Conference, 2009

Compiler assisted runtime task scheduling on a reconfigurable computer.
Proceedings of the 19th International Conference on Field Programmable Logic and Applications, 2009

A clustering framework for task partitioning based on function-level data usage analysis.
Proceedings of the ACM/SIGDA 17th International Symposium on Field Programmable Gate Arrays, 2009

Data path Configuration Time Reduction for Run-time Reconfigurable Systems.
Proceedings of the 2009 International Conference on Engineering of Reconfigurable Systems & Algorithms, 2009

Toward a runtime system for reconfigurable computers: A virtualization approach.
Proceedings of the Design, Automation and Test in Europe, 2009

Algorithms for the automatic extension of an instruction-set.
Proceedings of the Design, Automation and Test in Europe, 2009

A Multipurpose Clustering Algorithm for Task Partitioning in Multicore Reconfigurable Systems.
Proceedings of the 2009 International Conference on Complex, 2009

Hybrid Resource Discovery Mechanism in Ad Hoc Grid Using Structured Overlay.
Proceedings of the Architecture of Computing Systems, 2009

Online Task Scheduling for the FPGA-Based Partially Reconfigurable Systems.
Proceedings of the Reconfigurable Computing: Architectures, 2009

2008
Market Formulation for Resources Allocation in an Ad-Hoc Grid.
Proceedings of the Second IEEE International Conference on Self-Adaptive and Self-Organizing Systems, 2008

Self-Organizing Dynamic Ad Hoc Grids.
Proceedings of the Second IEEE International Conference on Self-Adaptive and Self-Organizing Systems, 2008

System-Level Design Space Exploration of Dynamic Reconfigurable Architectures.
Proceedings of the Embedded Computer Systems: Architectures, 2008

Clustering method for the identification of convex disconnected Multiple Input Multiple Output instructions.
Proceedings of the 2008 International Conference on Embedded Computer Systems: Architectures, 2008

Automatic Instruction-Set Extensions with the Linear Complexity Spiral Search.
Proceedings of the ReConFig'08: 2008 International Conference on Reconfigurable Computing and FPGAs, 2008

A self-adaptive on-line task placement algorithm for partially reconfigurable systems.
Proceedings of the 22nd IEEE International Symposium on Parallel and Distributed Processing, 2008

High level quantitative interconnect estimation for Early Design Space Exploration.
Proceedings of the 2008 International Conference on Field-Programmable Technology, 2008

Resource allocation algorithm and OpenMP extensions for parallel execution on a heterogeneous reconfigurable platform.
Proceedings of the FPL 2008, 2008

Loop unrolling and shifting for reconfigurable architectures.
Proceedings of the FPL 2008, 2008

Auction Protocols for Resource Allocations in Ad-Hoc Grids.
Proceedings of the Euro-Par 2008, 2008

Acceleration of Smith-Waterman using Recursive Variable Expansion.
Proceedings of the 11th Euromicro Conference on Digital System Design: Architectures, 2008

Intelligent Merging Online Task Placement Algorithm for Partial Reconfigurable Systems.
Proceedings of the Design, Automation and Test in Europe, 2008

An efficient algorithm for free resources management on the FPGA.
Proceedings of the Design, Automation and Test in Europe, 2008

Adaptation to Dynamic Resource Availability in Ad Hoc Grids through a Learning Mechanism.
Proceedings of the 11th IEEE International Conference on Computational Science and Engineering, 2008

Online Hardware Task Scheduling and Placement Algorithm on Partially Reconfigurable Devices.
Proceedings of the Reconfigurable Computing: Architectures, 2008

A Framework for the Automatic Generation of Instruction-Set Extensions for Reconfigurable Architectures.
Proceedings of the Reconfigurable Computing: Architectures, 2008

Optimal Unroll Factor for Reconfigurable Architectures.
Proceedings of the Reconfigurable Computing: Architectures, 2008

2007
The Molen compiler for reconfigurable processors.
ACM Trans. Embed. Comput. Syst., 2007

A Linear Complexity Algorithm for the Generation of Multiple Input Single Output Instructions of Variable Size.
Proceedings of the Embedded Computer Systems: Architectures, 2007

A Two-phase Practical Parallel Algorithm for Construction of Huffman Codes.
Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 2007

Fair access to scarce resources in ad-hoc grids using an economic-based approach.
Proceedings of the 5th International Workshop on Middleware for Grid Computing (MGC 2007), 2007

Automated HDL Generation: Comparative Evaluation.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

Performance Evaluation of Real-Time Message Delivery in RDM Algorithm.
Proceedings of the Third International Conference on Networking and Services (ICNS 2007), 2007

Recursive Variable Expansion: A Loop Transformation for Reconfigurable Systems.
Proceedings of the 2007 International Conference on Field-Programmable Technology, 2007

The Spiral Search: A Linear Complexity Algorithm for the Generation of Convex MIMO Instruction-Set Extensions.
Proceedings of the 2007 International Conference on Field-Programmable Technology, 2007

DWARV: DelftWorkBench Automated Reconfigurable VHDL Generator.
Proceedings of the FPL 2007, 2007


A Quantitative Prediction Model for Hardware/Software Partitioning.
Proceedings of the FPL 2007, 2007

HARTES Toolchain Early Evaluation: Profiling, Compilation and HDL Generation.
Proceedings of the FPL 2007, 2007

Resource Allocation in Market-based Grids Using a History-based Pricing Mechanism.
Proceedings of the Advances in Computer and Information Sciences and Engineering, 2007

A Linear Complexity Algorithm for the Automatic Generation of Convex Multiple Input Multiple Output Instructions.
Proceedings of the Reconfigurable Computing: Architectures, 2007

A Dynamic Pricing and Bidding Strategy for Autonomous Agents in Grids.
Proceedings of the Agents and Peer-to-Peer Computing, 6th International Workshop, 2007

2006
Interprocedural Compiler Optimization for Partial Run-Time Reconfiguration.
J. VLSI Signal Process., 2006

Market-Based Resource Allocation in Grids.
Proceedings of the Second International Conference on e-Science and Grid Technologies (e-Science 2006), 2006

Compiler-driven FPGA-area allocation for reconfigurable computing.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006

Automatic selection of application-specific instruction-set extensions.
Proceedings of the 4th International Conference on Hardware/Software Codesign and System Synthesis, 2006

PISC: Polymorphic Instruction Set Computers.
Proceedings of the Reconfigurable Computing: Architectures and Applications, 2006

2005
Interprocedural Optimization for Dynamic Hardware Configurations.
Proceedings of the Embedded Computer Systems: Architectures, 2005

Resource allocation on the grid: the GRAPPA approach.
Proceedings of the International Conference on Pervasive Services 2005, 2005

Instruction Scheduling for Dynamic Hardware Configurations.
Proceedings of the 2005 Design, 2005

2004
The MOLEN Polymorphic Processor.
IEEE Trans. Computers, 2004

The Molen Programming Paradigm.
Proceedings of the Computer Systems: Architectures, 2004

Dynamic Hardware Reconfigurations: Performance Impact for MPEG2.
Proceedings of the Computer Systems: Architectures, 2004

The PowerPC Backend Molen Compiler.
Proceedings of the Field Programmable Logic and Application, 2004

2003
Heterogeneous trading agents.
Complex., 2003

Compiling for the Molen Programming Paradigm.
Proceedings of the Field Programmable Logic and Application, 13th International Conference, 2003

2001
Agent-Based Social Simulation in Markets.
Electron. Commer. Res., 2001

On Chaos and Neural Networks: The Backpropagation Paradigm.
Artif. Intell. Rev., 2001

2000
A look inside the learning process of neural networks.
Complex., 2000

1999
Qualitative company performance evaluation: Linear discriminant analysis and neural network models.
Eur. J. Oper. Res., 1999

1998
Chaos and Neural Network Learning. Some Observations.
Neural Process. Lett., 1998

1996
2-1 Additions and Related Arithmetic Operations with Threshold Logic.
IEEE Trans. Computers, 1996

CAMUS: A Cognitive Model for Reverse Engineering-Bases Program Analysis.
Proceedings of the 8th Annual Workshop of the Psychology of Programming Interest Group, 1996

1995
XOR and backpropagation learning: in and out of the chaos?
Proceedings of the ESANN 1995, 1995

1993
A Cognitive Approach to Program Understanding.
Proceedings of Working Conference on Reverse Engineering, 1993

1992
A Cognitive Model of Programming Knowledge for Procedural Languages.
Proceedings of the Computer Assisted Learning, 4th International Conference, 1992


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