Giacomo Castoro

Orcid: 0000-0002-8963-1575

According to our database1, Giacomo Castoro authored at least 6 papers between 2023 and 2024.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

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PhD thesis 
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Bibliography

2024
10.6 A 10GHz FMCW Modulator Achieving 680MHz/μs Chirp Slope and 150kHz rms Frequency Error Based on a Digital-PLL with a Non-Uniform Piecewise-Parabolic Digital Predistortion.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024

10.1 An 8.75GHz Fractional-N Digital PLL with a Reverse-Concavity Variable-Slope DTC Achieving 57.3fsrms Integrated Jitter and -252.4dB FoM.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024

2023
A Low-Spur and Low-Jitter Fractional-N Digital PLL Based on an Inverse-Constant-Slope DTC and FCW Subtractive Dithering.
IEEE J. Solid State Circuits, December, 2023

Phase Noise Analysis of Periodically ON/OFF Switched Oscillators.
IEEE Trans. Circuits Syst. I Regul. Pap., January, 2023

A 76.7fs-lntegrated-Jitter and -71.9dBc In-Band Fractional-Spur Bang-Bang Digital PLL Based on an Inverse-Constant-Slope DTC and FCW Subtractive Dithering.
Proceedings of the IEEE International Solid- State Circuits Conference, 2023

A 9.25GHz Digital PLL with Fractional-Spur Cancellation Based on a Multi-DTC Topology.
Proceedings of the IEEE International Solid- State Circuits Conference, 2023


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