Luca Bertulessi

According to our database1, Luca Bertulessi authored at least 9 papers between 2018 and 2020.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

Online presence:

On csauthors.net:

Bibliography

2020
A 66-fs-rms Jitter 12.8-to-15.2-GHz Fractional-N Bang-Bang PLL With Digital Frequency-Error Recovery for Fast Locking.
IEEE J. Solid State Circuits, 2020

17.2 A 66fsrmsJitter 12.8-to-15.2GHz Fractional-N Bang-Bang PLL with Digital Frequency-Error Recovery for Fast Locking.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020

17.5 A 12.5GHz Fractional-N Type-I Sampling PLL Achieving 58fs Integrated Jitter.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020

2019
A 30-GHz Digital Sub-Sampling Fractional- $N$ PLL With -238.6-dB Jitter-Power Figure of Merit in 65-nm LP CMOS.
IEEE J. Solid State Circuits, 2019

A 30GHz Digital Sub-Sampling Fractional-N PLL with 198fsrms Jitter in 65nm LP CMOS.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019

2018
A Background Calibration Technique to Control the Bandwidth of Digital PLLs.
IEEE J. Solid State Circuits, 2018

A 23-GHz Low-Phase-Noise Digital Bang-Bang PLL for Fast Triangular and Sawtooth Chirp Modulation.
IEEE J. Solid State Circuits, 2018

A 23GHz low-phase-noise digital bang-bang PLL for fast triangular and saw-tooth chirp modulation.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018

A low-phase-noise digital bang-bang PLL with fast lock over a wide lock range.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018


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