Minsuk Koo
Orcid: 0000-0003-2522-6754
According to our database1,
Minsuk Koo authored at least 13 papers
between 2016 and 2026.
Collaborative distances:
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Bibliography
2026
Voltage-Summation-Based Compute-in-Memory SRAM Macro With Input-Bit and Synaptic-Bit Slicing.
IEEE J. Emerg. Sel. Topics Circuits Syst., June, 2026
IEEE Access, 2026
2025
Real Time Scheduling Framework for Multi Object Detection via Spiking Neural Networks.
CoRR, January, 2025
Voltage-Summation-Based Compute-in-Memory Technology with Capacitive Synaptic Devices.
Adv. Intell. Syst., 2025
2024
Design of a 180 nm CMOS Neuron Circuit with Soft-Reset and Underflow Allowing for Loss-Less Hardware Spiking Neural Networks.
Adv. Intell. Syst., January, 2024
Proceedings of the Pattern Recognition - 27th International Conference, 2024
Proceedings of the Pattern Recognition - 27th International Conference, 2024
2021
IMPULSE: A 65nm Digital Compute-in-Memory Macro with Fused Weights and Membrane Potential for Spike-based Sequential Learning Tasks.
CoRR, 2021
2020
IEEE Trans. Very Large Scale Integr. Syst., 2020
sBSNN: Stochastic-Bits Enabled Binary Spiking Neural Network With On-Chip Learning for Energy Efficient Neuromorphic Computing at the Edge.
IEEE Trans. Circuits Syst. I Regul. Pap., 2020
2019
IEEE Trans. Very Large Scale Integr. Syst., 2019
2017
Energy efficient computation using injection locked bias-field free spin-hall nano-oscillator array with shared heavy metal.
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2017
2016
Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016