Gregorio Cappuccino
Orcid: 0000-0001-8838-3525Affiliations:
- Universita della Calabria, Cosenza, Italy
According to our database1,
Gregorio Cappuccino
authored at least 28 papers
between 1998 and 2014.
Collaborative distances:
Collaborative distances:
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Bibliography
2014
Design of a 75-nW, 0.5-V subthreshold complementary metal-oxide-semiconductor operational amplifier.
Int. J. Circuit Theory Appl., 2014
2012
Int. J. Circuit Theory Appl., 2012
Int. J. Circuit Theory Appl., 2012
Special session: IEEE Real World Engineering Projects: Discovery-based curriculum modules for first-year students.
Proceedings of the IEEE Frontiers in Education Conference, 2012
2011
Int. J. Circuit Theory Appl., 2011
2010
Corrections to "Settling Time Optimization for Three-Stage CMOS Amplifier Topologies" [Dec 09 2569-2582].
IEEE Trans. Circuits Syst. I Regul. Pap., 2010
Analysis of the Impact of High-Order Integrator Dynamics on SC Sigma-Delta Modulator Performances.
IEEE Trans. Circuits Syst. I Regul. Pap., 2010
Microelectron. J., 2010
2009
IEEE Trans. Circuits Syst. I Regul. Pap., 2009
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009
Proceedings of the 16th IEEE International Conference on Electronics, 2009
Design considerations for fast-settling two-stage Miller-compensated operational amplifiers.
Proceedings of the 16th IEEE International Conference on Electronics, 2009
2008
Design Procedure for Settling Time Minimization in Three-Stage Nested-Miller Amplifiers.
IEEE Trans. Circuits Syst. II Express Briefs, 2008
Settling-Optimization-Based Design Approach for Three-Stage Nested-Miller Amplifiers.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2008
2007
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2007
Proceedings of the 2nd Internationa ICST Conference on Nano-Networks, 2007
Proceedings of the 18th European Conference on Circuit Theory and Design, 2007
2006
Correct Modelling of Nested Miller Compensated Amplifier for Discrete-Time Applications.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2006
A Simple MOSFET Parasitic Capacitance Model and Its Application to Repeater Insertion Technique.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2006
2005
Output Resistance Scaling Model for Deep-Submicron Cmos Buffers for Timing Performance Optimisation.
Proceedings of the Integrated Circuit and System Design, 2005
2003
Operating mode analysis of deep-submicron CMOS buffers driving inductive interconnects.
Proceedings of the 2003 10th IEEE International Conference on Electronics, 2003
Operating Region Modelling of Deep-submicron CMOS Buffers Driving Global Scope Inductive Interconnects.
Proceedings of the 2003 Euromicro Symposium on Digital Systems Design (DSD 2003), 2003
2002
Operating Region Modelling and Timing Analysis of CMOS Gates Driving Transmission Lines.
Proceedings of the Integrated Circuit Design. Power and Timing Modeling, 2002
2001
VLSI implementation of a fully static CMOS 56-bit self-timed adder using overlapped execution circuits.
Proceedings of the 2001 8th IEEE International Conference on Electronics, 2001
Proceedings of the 2001 8th IEEE International Conference on Electronics, 2001
Proceedings of the Conference on Design, Automation and Test in Europe, 2001
1999
A Time-Domain Model for Power Dissipation of CMOS Buffers Driving Lossy Transmission Lines.
Proceedings of the 25th EUROMICRO '99 Conference, 1999
1998
Microprocess. Microsystems, 1998