Gregorio Cappuccino
According to our database^{1},
Gregorio Cappuccino
authored at least 26 papers
between 1998 and 2014.
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Bibliography
2014
Design of a 75nW, 0.5V subthreshold complementary metaloxidesemiconductor operational amplifier.
Int. J. Circuit Theory Appl., 2014
2012
Int. J. Circuit Theory Appl., 2012
Int. J. Circuit Theory Appl., 2012
Special session: IEEE Real World Engineering Projects: Discoverybased curriculum modules for firstyear students.
Proceedings of the IEEE Frontiers in Education Conference, 2012
2011
Int. J. Circuit Theory Appl., 2011
2010
Corrections to "Settling Time Optimization for ThreeStage CMOS Amplifier Topologies" [Dec 09 25692582].
IEEE Trans. Circuits Syst. I Regul. Pap., 2010
Analysis of the Impact of HighOrder Integrator Dynamics on SC SigmaDelta Modulator Performances.
IEEE Trans. Circuits Syst. I Regul. Pap., 2010
Microelectron. J., 2010
2009
IEEE Trans. Circuits Syst. I Regul. Pap., 2009
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009
Proceedings of the 16th IEEE International Conference on Electronics, 2009
Design considerations for fastsettling twostage Millercompensated operational amplifiers.
Proceedings of the 16th IEEE International Conference on Electronics, 2009
2008
Design Procedure for Settling Time Minimization in ThreeStage NestedMiller Amplifiers.
IEEE Trans. Circuits Syst. II Express Briefs, 2008
SettlingOptimizationBased Design Approach for ThreeStage NestedMiller Amplifiers.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2008
2007
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2007
Proceedings of the 2nd Internationa ICST Conference on NanoNetworks, 2007
Proceedings of the 18th European Conference on Circuit Theory and Design, 2007
2006
Correct Modelling of Nested Miller Compensated Amplifier for DiscreteTime Applications.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2006
A Simple MOSFET Parasitic Capacitance Model and Its Application to Repeater Insertion Technique.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2006
2005
Output Resistance Scaling Model for DeepSubmicron Cmos Buffers for Timing Performance Optimisation.
Proceedings of the Integrated Circuit and System Design, 2005
2003
Operating mode analysis of deepsubmicron CMOS buffers driving inductive interconnects.
Proceedings of the 2003 10th IEEE International Conference on Electronics, 2003
Operating Region Modelling of Deepsubmicron CMOS Buffers Driving Global Scope Inductive Interconnects.
Proceedings of the 2003 Euromicro Symposium on Digital Systems Design (DSD 2003), 2003
2002
Operating Region Modelling and Timing Analysis of CMOS Gates Driving Transmission Lines.
Proceedings of the Integrated Circuit Design. Power and Timing Modeling, 2002
2001
Proceedings of the Conference on Design, Automation and Test in Europe, 2001
1999
A TimeDomain Model for Power Dissipation of CMOS Buffers Driving Lossy Transmission Lines.
Proceedings of the 25th EUROMICRO '99 Conference, 1999
1998
Microprocess. Microsystems, 1998