Gregorio Cappuccino

According to our database1, Gregorio Cappuccino authored at least 26 papers between 1998 and 2014.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

Online presence:

On csauthors.net:

Bibliography

2014
Design of a 75-nW, 0.5-V subthreshold complementary metal-oxide-semiconductor operational amplifier.
Int. J. Circuit Theory Appl., 2014

2012
A new efficient SC integrator scheme for high-speed low-power applications.
Int. J. Circuit Theory Appl., 2012

Design approach for high-bandwidth low-power three-stage operational amplifiers.
Int. J. Circuit Theory Appl., 2012

Special session: IEEE Real World Engineering Projects: Discovery-based curriculum modules for first-year students.
Proceedings of the IEEE Frontiers in Education Conference, 2012

2011
Design criterion for high-speed low-power SC circuits.
Int. J. Circuit Theory Appl., 2011

2010
Corrections to "Settling Time Optimization for Three-Stage CMOS Amplifier Topologies" [Dec 09 2569-2582].
IEEE Trans. Circuits Syst. I Regul. Pap., 2010

Analysis of the Impact of High-Order Integrator Dynamics on SC Sigma-Delta Modulator Performances.
IEEE Trans. Circuits Syst. I Regul. Pap., 2010

Analysis of op-amp phase margin impact on SC SigmaDelta modulator performance.
Microelectron. J., 2010

2009
Settling Time Optimization for Three-Stage CMOS Amplifier Topologies.
IEEE Trans. Circuits Syst. I Regul. Pap., 2009

Effect of OP-amp Phase Margin on SC SigmaDelta Modulator Performances.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

Class-AB output stage design for high-speed three-stage op-amps.
Proceedings of the 16th IEEE International Conference on Electronics, 2009

Design considerations for fast-settling two-stage Miller-compensated operational amplifiers.
Proceedings of the 16th IEEE International Conference on Electronics, 2009

2008
Design Procedure for Settling Time Minimization in Three-Stage Nested-Miller Amplifiers.
IEEE Trans. Circuits Syst. II Express Briefs, 2008

Settling-Optimization-Based Design Approach for Three-Stage Nested-Miller Amplifiers.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2008

2007
Settling Time Minimization of Operational Amplifiers.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2007

Integrated waveguides for ultra-high speed interconnects.
Proceedings of the 2nd Internationa ICST Conference on Nano-Networks, 2007

Design methodology of nested-Miller amplifiers for small capacitive loads.
Proceedings of the 18th European Conference on Circuit Theory and Design, 2007

2006
Correct Modelling of Nested Miller Compensated Amplifier for Discrete-Time Applications.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2006

A Simple MOSFET Parasitic Capacitance Model and Its Application to Repeater Insertion Technique.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2006

2005
Output Resistance Scaling Model for Deep-Submicron Cmos Buffers for Timing Performance Optimisation.
Proceedings of the Integrated Circuit and System Design, 2005

2003
Operating mode analysis of deep-submicron CMOS buffers driving inductive interconnects.
Proceedings of the 2003 10th IEEE International Conference on Electronics, 2003

Operating Region Modelling of Deep-submicron CMOS Buffers Driving Global Scope Inductive Interconnects.
Proceedings of the 2003 Euromicro Symposium on Digital Systems Design (DSD 2003), 2003

2002
Operating Region Modelling and Timing Analysis of CMOS Gates Driving Transmission Lines.
Proceedings of the Integrated Circuit Design. Power and Timing Modeling, 2002

2001
CMOS sizing rule for high performance long interconnects.
Proceedings of the Conference on Design, Automation and Test in Europe, 2001

1999
A Time-Domain Model for Power Dissipation of CMOS Buffers Driving Lossy Transmission Lines.
Proceedings of the 25th EUROMICRO '99 Conference, 1999

1998
High performance VLSI modules for division and square root.
Microprocess. Microsystems, 1998


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