Felice Crupi
Orcid: 0000-0002-5011-6621
According to our database1,
Felice Crupi
authored at least 65 papers
between 2002 and 2023.
Collaborative distances:
Collaborative distances:
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Bibliography
2023
Efficiency of Double-Barrier Magnetic Tunnel Junction-Based Digital eNVM Array for Neuro-Inspired Computing.
IEEE Trans. Circuits Syst. II Express Briefs, March, 2023
Experimental analysis of variability in WS<sub>2</sub>-based devices for hardware security.
CoRR, 2023
SIMPLY+: A Reliable STT-MRAM-Based Smart Material Implication Architecture for In-Memory Computing.
IEEE Access, 2023
Voltage Reference With Corner-Aware Replica Selection/Merging for 1.4-mV Accuracy in Harvested Systems Down to 3.9 pW, 0.2 V.
IEEE Access, 2023
2022
IEEE Trans. Circuits Syst. II Express Briefs, 2022
Analysis of Signal Processing Methods to Reject the DC Offset Contribution of Static Reflectors in FMCW Radar-Based Vital Signs Monitoring.
Sensors, 2022
Modified FMCW Scheme for Improved Ultrasonic Positioning and Ranging of Unmanned Ground Vehicles at Distances < 50 mm.
Sensors, 2022
Static CMOS Physically Unclonable Function Based on 4T Voltage Divider With 0.6%-1.5% Bit Instability at 0.4-1.8 V Operation in 180 nm.
IEEE J. Solid State Circuits, 2022
Smart Material Implication Using Spin-Transfer Torque Magnetic Tunnel Junctions for Logic-in-Memory Computing.
CoRR, 2022
Adjusting Thermal Stability in Double-Barrier MTJ for Energy Improvement in Cryogenic STT-MRAMs.
CoRR, 2022
Voltage-to-Voltage Sigmoid Neuron Activation Function Design for Artificial Neural Networks.
Proceedings of the 13th IEEE Latin America Symposium on Circuits and System, 2022
Stability-Area Trade-off in Static CMOS PUF Based on 4T Subthreshold Voltage Divider.
Proceedings of the 29th IEEE International Conference on Electronics, Circuits and Systems, 2022
2021
IEEE Trans. Circuits Syst. II Express Briefs, 2021
IEEE Trans. Circuits Syst. II Express Briefs, 2021
Trimming-Less Voltage Reference for Highly Uncertain Harvesting Down to 0.25 V, 5.4 pW.
IEEE J. Solid State Circuits, 2021
Proceedings of the IEEE International Conference on Smart Internet of Things, 2021
A 3.2-pW, 0.2-V Trimming-Less Voltage Reference with 1.4-mV Across-Wafer Total Accuracy.
Proceedings of the 47th ESSCIRC 2021, 2021
2020
Assessment of STT-MRAMs based on double-barrier MTJs for cache applications by means of a device-to-system level simulation framework.
Integr., 2020
A 0.25-V, 5.3-pW Voltage Reference with 25-μV/°C Temperature Coefficient, 140-μV/V Line Sensitivity and 2, 200-μm<sup>2</sup> Area in 180nm.
Proceedings of the IEEE Symposium on VLSI Circuits, 2020
2019
Proceedings of the 16th International Conference on Synthesis, 2019
Making IoT Services Accountable: A Solution Based on Blockchain and Physically Unclonable Functions.
Proceedings of the Internet and Distributed Computing Systems, 2019
An Energy Aware Variation-Tolerant Writing Termination Control for STT-based Non Volatile Flip-Flops.
Proceedings of the 26th IEEE International Conference on Electronics, Circuits and Systems, 2019
Proceedings of the 26th IEEE International Conference on Electronics, Circuits and Systems, 2019
Proceedings of the 49th European Solid-State Device Research Conference, 2019
Evaluating the Energy Efficiency of STT-MRAMs Based on Perpendicular MTJs with Double Reference Layers.
Proceedings of the 13th IEEE International Conference on ASIC, 2019
2018
A Variation-Aware Timing Modeling Approach for Write Operation in Hybrid CMOS/STT-MTJ Circuits.
IEEE Trans. Circuits Syst. I Regul. Pap., 2018
A portable class of 3-transistor current references with low-power sub-0.5 V operation.
Int. J. Circuit Theory Appl., 2018
Impact of the Emitter Contact Pattern in c-Si BC- BJ Solar Cells by Numerical Simulations.
Proceedings of the 4th IEEE International Forum on Research and Technology for Society and Industry, 2018
Proceedings of the 2018 International Conference on IC Design & Technology, 2018
2017
IEEE Trans. Circuits Syst. II Express Briefs, 2017
Int. J. Circuit Theory Appl., 2017
Int. J. Circuit Theory Appl., 2017
Impact of voltage scaling on STT-MRAMs through a variability-aware simulation framework.
Proceedings of the 14th International Conference on Synthesis, 2017
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017
Proceedings of the 2017 European Conference on Circuit Theory and Design, 2017
2015
IEEE Trans. Very Large Scale Integr. Syst., 2015
A sub-1 V nanopower temperature-compensated sub-threshold CMOS voltage reference with 0.065%/V line sensitivity.
Int. J. Circuit Theory Appl., 2015
Gate-level body biasing for subthreshold logic circuits: analytical modeling and design guidelines.
Int. J. Circuit Theory Appl., 2015
Proceedings of the IEEE International Reliability Physics Symposium, 2015
2014
Design of a 75-nW, 0.5-V subthreshold complementary metal-oxide-semiconductor operational amplifier.
Int. J. Circuit Theory Appl., 2014
Int. J. Circuit Theory Appl., 2014
Analysis of TFET based 6T SRAM cells implemented with state of the art silicon nanowires.
Proceedings of the 44th European Solid State Device Research Conference, 2014
2013
Impact of Al2O3 position on performances and reliability in high-k metal gated DRAM periphery transistors.
Proceedings of the European Solid-State Device Research Conference, 2013
2012
Buried Silicon-Germanium pMOSFETs: Experimental Analysis in VLSI Logic Circuits Under Aggressive Voltage Scaling.
IEEE Trans. Very Large Scale Integr. Syst., 2012
Understanding the Basic Advantages of Bulk FinFETs for Sub- and Near-Threshold Logic Circuits From Device Measurements.
IEEE Trans. Circuits Syst. II Express Briefs, 2012
Microelectron. Reliab., 2012
Microelectron. Reliab., 2012
Superior reliability and reduced Time-Dependent variability in high-mobility SiGe channel pMOSFETs for VLSI logic applications.
Proceedings of the IEEE International Conference on IC Design & Technology, 2012
Low-frequency noise assessment of the transport mechanisms in SiGe channel bulk FinFETs.
Proceedings of the 2012 European Solid-State Device Research Conference, 2012
2011
Understanding the Potential and the Limits of Germanium pMOSFETs for VLSI Circuits From Experimental Measurements.
IEEE Trans. Very Large Scale Integr. Syst., 2011
IEEE J. Solid State Circuits, 2011
Experimental analysis of buried SiGe pMOSFETs from the perspective of aggressive voltage scaling.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011
2010
Experimental study of leakage-delay trade-off in Germanium pMOSFETs for logic circuits.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010
2009
IEEE Trans. Circuits Syst. I Regul. Pap., 2009
Int. J. Circuit Theory Appl., 2009
2008
IEEE Trans. Instrum. Meas., 2008
2007
A New Circuit Topology for the Realization of Very Low-Noise Wide-Bandwidth Transimpedance Amplifier.
IEEE Trans. Instrum. Meas., 2007
Interfacial layer quality effects on low-frequency noise (1/f) in p-MOSFETs with advanced gate stacks.
Microelectron. Reliab., 2007
Low frequency noise in nMOSFETs with subnanometer EOT hafnium-based gate dielectrics.
Microelectron. Reliab., 2007
2006
IEEE Trans. Instrum. Meas., 2006
How to enlarge the bandwidth without increasing the noise in OP-AMP-based transimpedance amplifier.
IEEE Trans. Instrum. Meas., 2006
2004
Extraction of the trap distribution responsible for SILCs in MOS structures from the measurements and simulations of DC and noise properties.
Microelectron. Reliab., 2004
2003
IEEE Trans. Instrum. Meas., 2003
IEEE Trans. Instrum. Meas., 2003
2002
IEEE Trans. Instrum. Meas., 2002