Guilherme Bontorin

According to our database1, Guilherme Bontorin authored at least 11 papers between 2007 and 2019.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2019
A New Nonlinear Global Placement for FPGAs: The Chaotic Place.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019

2018
Reducing the amount of transistors by gate merging.
Proceedings of the 9th IEEE Latin American Symposium on Circuits & Systems, 2018

A nonlinear placement for FPGAs: The chaotic place.
Proceedings of the 9th IEEE Latin American Symposium on Circuits & Systems, 2018

2016
DHyANA: A NoC-based neural network hardware architecture.
Proceedings of the 2016 IEEE International Conference on Electronics, Circuits and Systems, 2016

2015
Energy-efficient Level Shifter topology.
Proceedings of the 25th International Workshop on Power and Timing Modeling, 2015

Overhead for independent net approach for Global Routing.
Proceedings of the IEEE 6th Latin American Symposium on Circuits & Systems, 2015

Low Latency FPGA Implementation of Izhikevich-Neuron Model.
Proceedings of the System Level Design from HW/SW to Memory for Embedded Systems, 2015

2014
Exploring more efficient architectures for Multiple Dynamic Supply Voltage designs.
Proceedings of the IEEE 5th Latin American Symposium on Circuits and Systems, 2014

2013
A novel approach to reduce power consumption in level shifter for Multiple Dynamic Supply Voltage.
Proceedings of the 20th IEEE International Conference on Electronics, 2013

2008
A real-time setup for multisite signal recording and processing in living neural networks.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

2007
Low noise and low cost neural amplifiers.
Proceedings of the 14th IEEE International Conference on Electronics, 2007


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