Cezar Reinbrecht

Orcid: 0000-0001-6113-7041

According to our database1, Cezar Reinbrecht authored at least 40 papers between 2008 and 2024.

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Bibliography

2024
Survey on Architectural Attacks: A Unified Classification and Attack Model.
ACM Comput. Surv., February, 2024

2023
A Survey on Machine Learning in Hardware Security.
ACM J. Emerg. Technol. Comput. Syst., April, 2023

A Pre-Silicon Power Leakage Assessment Based on Generative Adversarial Networks.
Proceedings of the 26th Euromicro Conference on Digital System Design, 2023

2022
Instruction flow-based detectors against fault injection attacks.
Microprocess. Microsystems, October, 2022

Exploiting PUF Variation to Detect Fault Injection Attacks.
Proceedings of the 25th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2022

2021
Applying Thermal Side-Channel Attacks on Asymmetric Cryptography.
IEEE Trans. Very Large Scale Integr. Syst., 2021

Multi-Bit Blinding: A Countermeasure for RSA Against Side Channel Attacks.
Proceedings of the 39th IEEE VLSI Test Symposium, 2021

Deterministic and Statistical Strategies to Protect ANNs against Fault Injection Attacks.
Proceedings of the 18th International Conference on Privacy, Security and Trust, 2021

LightRoAD: Lightweight Rowhammer Attack Detector.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2021

Impact of Data Pre-Processing Techniques on Deep Learning Based Power Attacks.
Proceedings of the 16th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2021

Protecting IoT Devices through a Hardware-driven Memory Verification.
Proceedings of the 24th Euromicro Conference on Digital System Design, 2021

Revealing the Secrets of Spiking Neural Networks: The Case of Izhikevich Neuron.
Proceedings of the 24th Euromicro Conference on Digital System Design, 2021

GRINCH: A Cache Attack against GIFT Lightweight Cipher.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

2020
S-NET: A Confusion Based Countermeasure Against Power Attacks for SBOX.
Proceedings of the Embedded Computer Systems: Architectures, Modeling, and Simulation, 2020

Guard-NoC: A Protection Against Side-Channel Attacks for MPSoCs.
Proceedings of the 2020 IEEE Computer Society Annual Symposium on VLSI, 2020

RNN-Based Detection of Fault Attacks on RSA.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

LiD-CAT: A Lightweight Detector for Cache ATtacks.
Proceedings of the IEEE European Test Symposium, 2020

G-PUF: An Intrinsic PUF Based on GPU Error Signatures.
Proceedings of the IEEE European Test Symposium, 2020

A Security Verification Template to Assess Cache Architecture Vulnerabilities.
Proceedings of the 23rd International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2020

2019
Cache timing attacks on NoC-based MPSoCs.
Microprocess. Microsystems, 2019

Side-channel protected MPSoC through secure real-time networks-on-chip.
Microprocess. Microsystems, 2019

Security Aspects of Real-Time MPSoCs: The Flaws and Opportunities of Preemptive NoCs.
Proceedings of the VLSI-SoC: New Technology Enabler, 2019

Attacking Real-time MPSoCs: Preemptive NoCs are Vulnerable.
Proceedings of the 27th IFIP/IEEE International Conference on Very Large Scale Integration, 2019

Towards Reliable and Secure Post-Quantum Co-Processors based on RISC-V.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

2018
Understanding MPSoCs: exploiting memory microarchitectural vulnerabilities of high performance NoC-based MPSoCs.
Proceedings of the 18th International Conference on Embedded Computer Systems: Architectures, 2018

Security aspects of neuromorphic MPSoCs.
Proceedings of the International Conference on Computer-Aided Design, 2018

Earthquake - A NoC-based optimized differential cache-collision attack for MPSoCs.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

2017
Timing attack on NoC-based systems: Prime+Probe attack and NoC-based protection.
Microprocess. Microsystems, 2017

2016
Side channel attack on NoC-based MPSoCs are practical: NoC Prime+Probe attack.
Proceedings of the 29th Symposium on Integrated Circuits and Systems Design, 2016

Gossip NoC - Avoiding Timing Side-Channel Attacks through Traffic Management.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016

DHyANA: A NoC-based neural network hardware architecture.
Proceedings of the 2016 IEEE International Conference on Electronics, Circuits and Systems, 2016

2015
PHiCIT: Improving Hierarchical Networks-on-chip through 3D Silicon Photonics Integration.
Proceedings of the 28th Symposium on Integrated Circuits and Systems Design, 2015

2014
Adaptive multiple switching strategy toward an ideal NoC.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

2013
A power-efficient hierarchical network-on-chip topology for stacked 3D ICs.
Proceedings of the 21st IEEE/IFIP International Conference on VLSI and System-on-Chip, 2013

Hierarchical and Multiple Switching NoC with Floorplan Based Adaptability.
Proceedings of the Reconfigurable Computing: Architectures, Tools and Applications, 2013

2012
Floorplan-aware hierarchical NoC topology with GALS interfaces.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

2011
Floorplanning-aware design space exploration for application-specific hierarchical networks on-chip.
Proceedings of the 4th International Workshop on Network on Chip Architectures, 2011

2009
A high abstraction, high accuracy power estimation model for networks-on-chip.
Proceedings of the 22st Annual Symposium on Integrated Circuits and Systems Design: Chip on the Dunes, 2009

Increasing NoC power estimation accuracy through a rate-based model.
Proceedings of the Third International Symposium on Networks-on-Chips, 2009

2008
NoC Power Estimation at the RTL Abstraction Level.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2008


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