Marcelo O. Johann

According to our database1, Marcelo O. Johann authored at least 44 papers between 1999 and 2019.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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PhD thesis 
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Bibliography

2019
An Optimized Cost Flow Algorithm to Spread Cells in Detailed Placement.
ACM Trans. Design Autom. Electr. Syst., 2019

Automatic Transcription of Diatonic Harmonica Recordings.
Proceedings of the IEEE International Conference on Acoustics, 2019

2018
A polyphonic pitch tracking embedded system for rapid instrument augmentation.
Proceedings of the 18th International Conference on New Interfaces for Musical Expression, 2018

2017
Rsyn: An Extensible Physical Synthesis Framework.
Proceedings of the 2017 ACM on International Symposium on Physical Design, 2017

2016
Improving placement algorithms by using visualization tools.
Proceedings of the 14th IEEE International New Circuits and Systems Conference, 2016

Routing-Aware Incremental Timing-Driven Placement.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016

Drive Strength Aware Cell Movement Techniques for Timing Driven Placement.
Proceedings of the 2016 on International Symposium on Physical Design, 2016

Quadratic timing objectives for incremental timing-driven placement optimization.
Proceedings of the 2016 IEEE International Conference on Electronics, Circuits and Systems, 2016

2015
An Incremental Timing-Driven flow using quadratic formulation for detailed placement.
Proceedings of the 2015 IFIP/IEEE International Conference on Very Large Scale Integration, 2015

Jezz: An Effective Legalization Algorithm for Minimum Displacement.
Proceedings of the 28th Symposium on Integrated Circuits and Systems Design, 2015

Energy-efficient Level Shifter topology.
Proceedings of the 25th International Workshop on Power and Timing Modeling, 2015

An analytical timing-driven algorithm for detailed placement.
Proceedings of the IEEE 6th Latin American Symposium on Circuits & Systems, 2015

Interaction Aesthetics and Ubiquitous Music.
Proceedings of the Creativity in the Digital Age., 2015

2014
Analogue Audio Recording Using Remote Servers.
Proceedings of the Ubiquitous Music, 2014

A Hybrid Technique for Discrete Gate Sizing Based on Lagrangian Relaxation.
ACM Trans. Design Autom. Electr. Syst., 2014

Effective Method for Simultaneous Gate Sizing and $V$ th Assignment Using Lagrangian Relaxation.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2014

Ecologically grounded multimodal design: The Palafito 1.0 study.
Proceedings of the Music Technology meets Philosophy, 2014

Relational Properties in Interaction Aesthetics: The Ubiquitous Music Turn.
Proceedings of the Electronic Visualisation and the Arts, 2014

2013
Recent advances and challenges in physical design automation.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2013

Simultaneous gate sizing and Vth assignment using Lagrangian Relaxation and delay sensitivities.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2013

Simultaneous gate sizing and Vt assignment using Fanin/Fanout ratio and Simulated Annealing.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

Fast and efficient lagrangian relaxation-based discrete gate sizing.
Proceedings of the Design, Automation and Test in Europe, 2013

2012
Posicionamento de Circuitos 3D Considerando o Planejamento de 3D-Vias.
RITA, 2012

A System for recording analog synthesizers with the Web.
Proceedings of the Non-Cochlear Sound: Proceedings of the 38th International Computer Music Conference, 2012

Lagrangian relaxation-based Discrete Gate Sizing for leakage power minimization.
Proceedings of the 19th IEEE International Conference on Electronics, Circuits and Systems, 2012

2011
Quadratic placement with single-iteration linear system solver.
Proceedings of the 24th Symposium on Integrated Circuits and Systems Design, 2011

2010
3D-Via Driven Partitioning for 3D VLSI Integrated Circuits.
CLEI Electron. J., 2010

Logical Core Algorithm: Improving Global Placement.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2010

A Mesh-Buffer Displacement Optimization Strategy.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2010

The Fidelity Property of the Elmore Delay Model in actual comparison of routing algorithms.
Proceedings of the 28th International Conference on Computer Design, 2010

2009
Maze Routing Steiner Trees With Delay Versus Wire Length Tradeoff.
IEEE Trans. VLSI Syst., 2009

A cells and I/O pins partitioning refinement algorithm for 3D VLSI circuits.
Proceedings of the 16th IEEE International Conference on Electronics, 2009

On the accuracy of Elmore-based Delay Models.
Proceedings of the 16th IEEE International Conference on Electronics, 2009

2007
Cell placement on graphics processing units.
Proceedings of the 20th Annual Symposium on Integrated Circuits and Systems Design, 2007

Maze routing steiner trees with effective critical sink optimization.
Proceedings of the 2007 International Symposium on Physical Design, 2007

2006
A Method for I/O Pins Partitioning Targeting 3D VLSI Circuits.
Proceedings of the VLSI-SoC: Research Trends in VLSI and Systems on Chip, 2006

An Algorithm for I/O Partitioning Targeting 3D Circuits and Its Impact on 3D-Vias.
Proceedings of the IFIP VLSI-SoC 2006, 2006

Channel based routing in channel-less circuits.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

Unbalacing the I/O Pins Partitioning for Minimizing Inter-Tier Vias in 3D VLSI Circuits.
Proceedings of the 13th IEEE International Conference on Electronics, 2006

2005
Blue Macaw: A Didactic Placement Tool Using Simulated Annealing.
Proceedings of the New Trends and Technologies in Computer-Aided Learning for Computer-Aided Design, 2005

2004
Design of Very Deep Pipelined Multipliers for FPGAs.
Proceedings of the 2004 Design, 2004

2003
A study on the performance of fast initial placement algorithms.
Proceedings of the IFIP VLSI-SoC 2003, 2003

2000
Admissibility Proofs for the LCS* Algorithm.
Proceedings of the Advances in Artificial Intelligence, 2000

1999
Designing a Mask Programmable Matrix for Sequential Circuits.
Proceedings of the VLSI: Systems on a Chip, 1999


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