Vitor V. Bandeira

Orcid: 0000-0001-7459-0072

According to our database1, Vitor V. Bandeira authored at least 13 papers between 2015 and 2022.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2022
SOFIA: An automated framework for early soft error assessment, identification, and mitigation.
J. Syst. Archit., 2022

Soft Error Reliability Assessment of Lightweight Cryptographic Algorithms for IoT Edge Devices.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

2021
An Extensive Soft Error Reliability Analysis of a Real Autonomous Vehicle Software Stack.
IEEE Trans. Circuits Syst. II Express Briefs, 2021

Evaluation of the soft error assessment consistency of a JIT-based virtual platform simulator.
IET Comput. Digit. Tech., 2021

2020
Fast and Scalable I/O Pin Assignment with Divide-and-Conquer and Hungarian Matching.
Proceedings of the 18th IEEE International New Circuits and Systems Conference, 2020

2019
Exploration of Techniques to Assess Soft Errors in Multicore Architectures.
Proceedings of the 27th IFIP/IEEE International Conference on Very Large Scale Integration, 2019

Non-intrusive Fault Injection Techniques for Efficient Soft Error Vulnerability Analysis.
Proceedings of the 27th IFIP/IEEE International Conference on Very Large Scale Integration, 2019

Efficient Soft Error Vulnerability Analysis Using Non-intrusive Fault Injection Techniques.
Proceedings of the VLSI-SoC: New Technology Enabler, 2019

Soft Error Reliability Analysis of Autonomous Vehicles Software Stack.
Proceedings of the 27th IFIP/IEEE International Conference on Very Large Scale Integration, 2019

Evaluation of Compilers Effects on OpenMP Soft Error Resiliency.
Proceedings of the 2019 IEEE Computer Society Annual Symposium on VLSI, 2019

2018
Extensive evaluation of programming models and ISAs impact on multicore soft error reliability.
Proceedings of the 55th Annual Design Automation Conference, 2018

2016
DHyANA: A NoC-based neural network hardware architecture.
Proceedings of the 2016 IEEE International Conference on Electronics, Circuits and Systems, 2016

2015
Low Latency FPGA Implementation of Izhikevich-Neuron Model.
Proceedings of the System Level Design from HW/SW to Memory for Embedded Systems, 2015


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