Haijun Liu

Orcid: 0000-0002-5094-5411

Affiliations:
  • National University of Defense Technology, College of Electronic Science and Technology, China (PhD 2010)
  • Shandong University of Technology, Zibo, China (former)


According to our database1, Haijun Liu authored at least 22 papers between 2011 and 2022.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

Online presence:

On csauthors.net:

Bibliography

2022
Fast and Reconfigurable Logic Synthesis in Memristor Crossbar Array.
Adv. Intell. Syst., December, 2022

CMQ: Crossbar-Aware Neural Network Mixed-Precision Quantization via Differentiable Architecture Search.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

In Situ Learning in Hardware Compatible Multilayer Memristive Spiking Neural Network.
IEEE Trans. Cogn. Dev. Syst., 2022

Error Detection and Correction Method Toward Fully Memristive Stateful Logic Design.
Adv. Intell. Syst., 2022

2021
Binary Memristive Synapse Based Vector Neural Network Architecture and Its Application.
IEEE Trans. Circuits Syst. II Express Briefs, 2021

In-situ learning in multilayer locally-connected memristive spiking neural network.
Neurocomputing, 2021

Logic Implementation Based on Double Memristors.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

2020
Implication of unsafe writing on the MAGIC NOR gate.
Microelectron. J., 2020

Enhanced Spiking Neural Network with forgetting phenomenon based on electronic synaptic devices.
Neurocomputing, 2020

Solution to alleviate the impact of line resistance on the crossbar array.
IET Circuits Devices Syst., 2020

Unsafe Writing Impacts on the Stateful Memristor Gates.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

2019
Quaternary synapses network for memristor-based spiking convolutional neural networks.
IEICE Electron. Express, 2019

A memristor-based convolutional neural network with full parallelization architecture.
IEICE Electron. Express, 2019

Cases Study of Inputs Split Based Calibration Method for RRAM Crossbar.
IEEE Access, 2019

Cascaded Architecture for Memristor Crossbar Array Based Larger-Scale Neuromorphic Computing.
IEEE Access, 2019

A TaO<sub>x</sub>-Based Electronic Synapse With High Precision for Neuromorphic Computing.
IEEE Access, 2019

Cascaded Neural Network for Memristor based Neuromorphic Computing.
Proceedings of the International Joint Conference on Neural Networks, 2019

2018
Low-Consumption Neuromorphic Memristor Architecture Based on Convolutional Neural Networks.
Proceedings of the 2018 International Joint Conference on Neural Networks, 2018

2017
Exploration of selector characteristic based on electron tunneling for RRAM array application.
IEICE Electron. Express, 2017

2016
Impact of electroforming polarity on <i>TiO</i><sub>2</sub> based memristor.
IEICE Electron. Express, 2016

2011
High Speed Real-Time Data Acquisition System Based on Solid-State Storage Technique.
Proceedings of the Second International Conference on Digital Manufacturing and Automation, 2011

Design and Implementation of the Accumulating Algorithm of Digital Signal Averager.
Proceedings of the Second International Conference on Digital Manufacturing and Automation, 2011


  Loading...