Hui Xu

Affiliations:
  • National University of Defense Technology, College of Electronic Science and Technology, Hunan, China


According to our database1, Hui Xu authored at least 48 papers between 2011 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2024
Input-Independent Array Compensation in Memristor-Arrays-Based Neuromorphic Systems for Input Resistance.
IEEE Trans. Circuits Syst. II Express Briefs, April, 2024

Efficient Parallel Polynomial-Based Compensation Structure for Frequency Response Mismatch in Two-Channel TI-ADCs.
IEEE Trans. Circuits Syst. II Express Briefs, February, 2024

2023
In-Sensor Reservoir Computing Based on Optoelectronic Synapse.
Adv. Intell. Syst., January, 2023

2022
Fast and Reconfigurable Logic Synthesis in Memristor Crossbar Array.
Adv. Intell. Syst., December, 2022

High-Speed Memristor-Based Ripple Carry Adders in 1T1R Array Structure.
IEEE Trans. Circuits Syst. II Express Briefs, 2022

In Situ Learning in Hardware Compatible Multilayer Memristive Spiking Neural Network.
IEEE Trans. Cogn. Dev. Syst., 2022

Error Detection and Correction Method Toward Fully Memristive Stateful Logic Design.
Adv. Intell. Syst., 2022

2021
In-situ learning in multilayer locally-connected memristive spiking neural network.
Neurocomputing, 2021

Energy-Efficient Memristive Euclidean Distance Engine for Brain-Inspired Competitive Learning.
Adv. Intell. Syst., 2021

A Symmetric Multilayer GeSe/GeSeSbTe Ovonic Threshold Switching Selector with Improved Endurance and Stability.
Proceedings of the 2021 IEEE International Conference on Integrated Circuits, 2021

MAGIC-Based Nonvolatile Binary Counters.
Proceedings of the IEEE Asia Pacific Conference on Circuit and Systems, 2021

2020
Correlation-Based Calibration for Nonlinearity Mismatches in Dual-Channel TIADCs.
IEEE Trans. Circuits Syst. II Express Briefs, 2020

Implication of unsafe writing on the MAGIC NOR gate.
Microelectron. J., 2020

Enhanced Spiking Neural Network with forgetting phenomenon based on electronic synaptic devices.
Neurocomputing, 2020

Solution to alleviate the impact of line resistance on the crossbar array.
IET Circuits Devices Syst., 2020

Unsafe Writing Impacts on the Stateful Memristor Gates.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

2019
Cases Study of Inputs Split Based Calibration Method for RRAM Crossbar.
IEEE Access, 2019

Cascaded Architecture for Memristor Crossbar Array Based Larger-Scale Neuromorphic Computing.
IEEE Access, 2019

Cascaded Neural Network for Memristor based Neuromorphic Computing.
Proceedings of the International Joint Conference on Neural Networks, 2019

2018
Statistics-Based Correction Method for Sample-and-Hold Mismatch in 2-Channel TIADCs.
Proceedings of the 41st International Conference on Telecommunications and Signal Processing, 2018

Low-Consumption Neuromorphic Memristor Architecture Based on Convolutional Neural Networks.
Proceedings of the 2018 International Joint Conference on Neural Networks, 2018

Hardware-Efficient Parallel FIR Filter Structure Based on Modified Cook-Toom Algorithm.
Proceedings of the 2018 IEEE Asia Pacific Conference on Circuits and Systems, 2018

2017
An Adaptive Blind Frequency-Response Mismatches Calibration Method for Four-Channel TIADCs Based on Channel Swapping.
IEEE Trans. Circuits Syst. II Express Briefs, 2017

An efficient blind calibration method for nonlinearity mis-matches in <i>M</i>-channel TIADCs.
IEICE Electron. Express, 2017

A compliance current circuit with nanosecond response time for ReRAM characterization.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

2016
An FPGA-Based Instrument for En-Masse RRAM Characterization With ns Pulsing Resolution.
IEEE Trans. Circuits Syst. I Regul. Pap., 2016

A memristor random circuit breaker model accounting for stimulus thermal accumulation.
IEICE Electron. Express, 2016

Impact of electroforming polarity on <i>TiO</i><sub>2</sub> based memristor.
IEICE Electron. Express, 2016

A calibration method for frequency response mismatches in <i>M</i>-channel time-interleaved analog-to-digital converters.
IEICE Electron. Express, 2016

Minimax design and order estimation of FIR filters for extending the bandwidth of ADCs.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

Integral Nonlinear Fitting and Calibration of High Precision Analog-Digital Converters.
Proceedings of the 13th International Conference on Embedded Software and Systems, 2016

2015
Joint Blind Calibration for Mixed Mismatches in Two-Channel Time-Interleaved ADCs.
IEEE Trans. Circuits Syst. I Regul. Pap., 2015

Adaptive Background Estimation for Static Nonlinearity Mismatches in Two-Channel TIADCs.
IEEE Trans. Circuits Syst. II Express Briefs, 2015

A Flash-aware Intra-disk Redundancy scheme for high reliable All Flash Array.
IEICE Electron. Express, 2015

Digital estimation and compensation method for nonlinearity mismatches in time-interleaved analog-to-digital converters.
Digit. Signal Process., 2015

Digital estimation and calibration algorithm for 2-order nonlinearity mismatch in time-interleaved sampling system.
Proceedings of the 38th International Conference on Telecommunications and Signal Processing, 2015

Impact of active areas on electrical characteristics of TiO2 based solid-state memristors.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

FPGA logic design of SATA3.0 physical layer.
Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015

2014
A new differential RAID for high reliable All Flash Array.
IEICE Electron. Express, 2014

Estimation method for nonlinearity mismatch in time-interleaved analog-to-digital converters.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

Origin of stochastic resistive switching in devices with phenomenologically identical initial states.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

Blind calibration of nonlinearity mismatch errors in two-channel time-interleaved ADCs.
Proceedings of the 21st IEEE International Conference on Electronics, Circuits and Systems, 2014

2013
Reconfigurable Bioimpedance Emulation System for Electrical Impedance Tomography System Validation.
IEEE Trans. Biomed. Circuits Syst., 2013

2012
A Group-Based Hybrid Wear-Leveling Algorithm for Flash Memory Storage Systems.
Proceedings of the Third International Conference on Digital Manufacturing & Automation, 2012

High Accuracy Biological Impedance Measurement System Design and Calibration.
Proceedings of the Third International Conference on Digital Manufacturing & Automation, 2012

2011
High Speed Real-Time Data Acquisition System Based on Solid-State Storage Technique.
Proceedings of the Second International Conference on Digital Manufacturing and Automation, 2011

Design of a novel digital phantom for EIT system calibration.
Proceedings of the 33rd Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2011

High-speed digital-controlled variable voltage source with current monitor for EIT application.
Proceedings of the 4th International Conference on Biomedical Engineering and Informatics, 2011


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