Zhiwei Li

Orcid: 0000-0002-6238-2660

Affiliations:
  • National University of Defense Technology, College of Electronic Science and Technology, Changsha, China
  • Arizona State University, School of Electrical, Computer and Energy Engineering, Tempe, AZ, USA


According to our database1, Zhiwei Li authored at least 26 papers between 2016 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2024
Efficient Parallel Polynomial-Based Compensation Structure for Frequency Response Mismatch in Two-Channel TI-ADCs.
IEEE Trans. Circuits Syst. II Express Briefs, February, 2024

2023
Unified Filter Order Estimate for Minimax-Designed Linear-Phase FIR Wideband and Lowpass Digital Differentiators.
Circuits Syst. Signal Process., November, 2023

AIMCU-MESO: An In-Memory Computing Unit Constructed by MESO Device.
ACM Trans. Design Autom. Electr. Syst., January, 2023

In-Sensor Reservoir Computing Based on Optoelectronic Synapse.
Adv. Intell. Syst., January, 2023

A High-speed and Low-power FPGA Implementation of Spiking Convolutional Neural Network Using Logarithmic Quantization.
Proceedings of the 19th International Conference on Natural Computation, 2023

2022
On the Compensation of Timing Mismatch in Two-Channel Time-Interleaved ADCs: Strategies and a Novel Parallel Compensation Structure.
IEEE Trans. Signal Process., 2022

High-Speed Memristor-Based Ripple Carry Adders in 1T1R Array Structure.
IEEE Trans. Circuits Syst. II Express Briefs, 2022

CMQ: Crossbar-Aware Neural Network Mixed-Precision Quantization via Differentiable Architecture Search.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

In Situ Learning in Hardware Compatible Multilayer Memristive Spiking Neural Network.
IEEE Trans. Cogn. Dev. Syst., 2022

Pipelined Memristive Analog-to-Digital Converter With Self-Adaptive Weight Tuning.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2022

Error Detection and Correction Method Toward Fully Memristive Stateful Logic Design.
Adv. Intell. Syst., 2022

2021
Binary Memristive Synapse Based Vector Neural Network Architecture and Its Application.
IEEE Trans. Circuits Syst. II Express Briefs, 2021

In-situ learning in multilayer locally-connected memristive spiking neural network.
Neurocomputing, 2021

Logic Implementation Based on Double Memristors.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

MAGIC-Based Nonvolatile Binary Counters.
Proceedings of the IEEE Asia Pacific Conference on Circuit and Systems, 2021

2020
Implication of unsafe writing on the MAGIC NOR gate.
Microelectron. J., 2020

Enhanced Spiking Neural Network with forgetting phenomenon based on electronic synaptic devices.
Neurocomputing, 2020

Solution to alleviate the impact of line resistance on the crossbar array.
IET Circuits Devices Syst., 2020

Unsafe Writing Impacts on the Stateful Memristor Gates.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

2019
Quaternary synapses network for memristor-based spiking convolutional neural networks.
IEICE Electron. Express, 2019

A memristor-based convolutional neural network with full parallelization architecture.
IEICE Electron. Express, 2019

Cases Study of Inputs Split Based Calibration Method for RRAM Crossbar.
IEEE Access, 2019

A TaO<sub>x</sub>-Based Electronic Synapse With High Precision for Neuromorphic Computing.
IEEE Access, 2019

2018
Low-Consumption Neuromorphic Memristor Architecture Based on Convolutional Neural Networks.
Proceedings of the 2018 International Joint Conference on Neural Networks, 2018

2016
Design Tradeoffs of Vertical RRAM-Based 3-D Cross-Point Array.
IEEE Trans. Very Large Scale Integr. Syst., 2016

A memristor random circuit breaker model accounting for stimulus thermal accumulation.
IEICE Electron. Express, 2016


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