Haile Yu

According to our database1, Haile Yu authored at least 11 papers between 2008 and 2012.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2012
An FPGA Chip Identification Generator Using Configurable Ring Oscillators.
IEEE Trans. Very Large Scale Integr. Syst., 2012

HTOutlier: Hardware Trojan detection with side-channel signature outlier identification.
Proceedings of the 2012 IEEE International Symposium on Hardware-Oriented Security and Trust, 2012

CODA: A concurrent online delay measurement architecture for critical paths.
Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012

2011
On Timing Yield Improvement for FPGA Designs Using Architectural Symmetry.
Proceedings of the International Conference on Field Programmable Logic and Applications, 2011

On timing yield improvement for FPGA designs using architectural symmetry (abstract only).
Proceedings of the ACM/SIGDA 19th International Symposium on Field Programmable Gate Arrays, 2011

2010
Fine-grained characterization of process variation in FPGAs.
Proceedings of the International Conference on Field-Programmable Technology, 2010

An FPGA chip identification generator using configurable ring oscillator.
Proceedings of the International Conference on Field-Programmable Technology, 2010

2009
A detailed delay path model for FPGAs.
Proceedings of the 2009 International Conference on Field-Programmable Technology, 2009

Towards a unique FPGA-based identification circuit using process variations.
Proceedings of the 19th International Conference on Field Programmable Logic and Applications, 2009

2008
FPGA interconnect sizing using extended logical effort model.
Proceedings of the FPL 2008, 2008

FPGA interconnect design using logical effort.
Proceedings of the ACM/SIGDA 16th International Symposium on Field Programmable Gate Arrays, 2008


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