Thomas C. P. Chau

Affiliations:
  • Neubla, UK
  • Samsung AI Center, Cambridge, UK (former)
  • Intel Corporation, High Wycombe, UK (former)
  • Altera, High Wycombe, UK (former)
  • Imperial College London, Department of Computing, UK (former, PhD 2014)
  • Chinese University of Hong Kong, Department of Computer Science and Engineering, Hong Kong (former)


According to our database1, Thomas C. P. Chau authored at least 34 papers between 2009 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

Online presence:

On csauthors.net:

Bibliography

2023
Zero-Cost Operation Scoring in Differentiable Architecture Search.
Proceedings of the Thirty-Seventh AAAI Conference on Artificial Intelligence, 2023

2022
BLOX: Macro Neural Architecture Search Benchmark and Algorithms.
Proceedings of the Advances in Neural Information Processing Systems 35: Annual Conference on Neural Information Processing Systems 2022, 2022

Adaptable Butterfly Accelerator for Attention-based NNs via Hardware and Algorithm Co-design.
Proceedings of the 55th IEEE/ACM International Symposium on Microarchitecture, 2022

2021
Zero-Cost Proxies Meet Differentiable Architecture Search.
CoRR, 2021

NAS-Bench-ASR: Reproducible Neural Architecture Search for Speech Recognition.
Proceedings of the 9th International Conference on Learning Representations, 2021

2020
BRP-NAS: Prediction-based NAS using GCNs.
Proceedings of the Advances in Neural Information Processing Systems 33: Annual Conference on Neural Information Processing Systems 2020, 2020

Codesign-NAS: Automatic FPGA/CNN Codesign Using Neural Architecture Search.
Proceedings of the FPGA '20: The 2020 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2020

Best of Both Worlds: AutoML Codesign of a CNN and its Hardware Accelerator.
Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020

2019
Transparent Heterogeneous Cloud Acceleration.
Proceedings of the 30th IEEE International Conference on Application-specific Systems, 2019

2018
Towards Hardware Accelerated Reinforcement Learning for Application-Specific Robotic Control.
Proceedings of the 29th IEEE International Conference on Application-specific Systems, 2018

2017
Chapter Two - Advances in Dataflow Systems.
Adv. Comput., 2017

2016
Hardware-in-the-loop simulation of FPGA-based state estimators for electric vehicle batteries.
Proceedings of the 25th IEEE International Symposium on Industrial Electronics, 2016

An FPGA-based platform for integrated power and motion control.
Proceedings of the IECON 2016, 2016

2015
Automating Elimination of Idle Functions by Runtime Reconfiguration.
ACM Trans. Reconfigurable Technol. Syst., 2015

Mapping Adaptive Particle Filters to Heterogeneous Reconfigurable Systems.
ACM Trans. Reconfigurable Technol. Syst., 2015

Recursive pipelined genetic propagation for bilevel optimisation.
Proceedings of the 25th International Conference on Field Programmable Logic and Applications, 2015

2014
Optimising reconfigurable systems for real-time applications.
PhD thesis, 2014

Automating Optimization of Reconfigurable Designs.
Proceedings of the 22nd IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2014

SMCGen: Generating Reconfigurable Design for Sequential Monte Carlo Applications.
Proceedings of the 22nd IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2014

2013
Architecture and Design Flow for a Highly Efficient Structured ASIC.
IEEE Trans. Very Large Scale Integr. Syst., 2013

Accelerating sequential Monte Carlo method for real-time air traffic management.
SIGARCH Comput. Archit. News, 2013

Acceleration of real-time Proximity Query for dynamic active constraints.
Proceedings of the 2013 International Conference on Field-Programmable Technology, 2013

Automating resource optimisation in reconfigurable design (abstract only).
Proceedings of the 2013 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2013

Automating Elimination of Idle Functions by Run-Time Reconfiguration.
Proceedings of the 21st IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2013

Parallelisation of Sequential Monte Carlo for real-time control in air traffic management.
Proceedings of the 52nd IEEE Conference on Decision and Control, 2013

Heterogeneous Reconfigurable System for Adaptive Particle Filters in Real-Time Applications.
Proceedings of the Reconfigurable Computing: Architectures, Tools and Applications, 2013

2012
Roberts: reconfigurable platform for benchmarking real-time systems.
SIGARCH Comput. Archit. News, 2012

Adaptive Sequential Monte Carlo approach for real-time applications.
Proceedings of the 22nd International Conference on Field Programmable Logic and Applications (FPL), 2012

2010
Structured ASIC: Methodology and comparison.
Proceedings of the International Conference on Field-Programmable Technology, 2010

Design of a single layer programmable Structured ASIC library.
Proceedings of the 13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2010

Rapid prototyping on a structured ASIC fabric.
Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010

2009
Generation of Synthetic Floating-Point benchmark circuits.
Proceedings of the 23rd IEEE International Symposium on Parallel and Distributed Processing, 2009

A detailed delay path model for FPGAs.
Proceedings of the 2009 International Conference on Field-Programmable Technology, 2009

A comparison of via-programmable gate array logic cell circuits.
Proceedings of the ACM/SIGDA 17th International Symposium on Field Programmable Gate Arrays, 2009


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