Hak-soo Yu

According to our database1, Hak-soo Yu authored at least 8 papers between 2000 and 2021.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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PhD thesis 
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Links

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Bibliography

2021
25.4 A 20nm 6GB Function-In-Memory DRAM, Based on HBM2 with a 1.2TFLOPS Programmable Computing Unit Using Bank-Level Parallelism, for Machine Learning Applications.
Proceedings of the IEEE International Solid-State Circuits Conference, 2021

2004
Performance Characterization of Mixed-Signal Circuits Using a Ternary Signal Representation.
Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004

LFSR-based BIST for analog circuits using slope detection.
Proceedings of the 14th ACM Great Lakes Symposium on VLSI 2004, 2004

An efficient linearity test for on-chip high speed ADC and DAC using loop-back.
Proceedings of the 14th ACM Great Lakes Symposium on VLSI 2004, 2004

2003
DSP-Based Statistical Self Test of On-Chip Converters.
Proceedings of the 21st IEEE VLSI Test Symposium (VTS 2003), 27 April, 2003

Efficient loop-back testing of on-chip ADCs and DACs.
Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003

2002
An Efficient 3-Bit -Scan Multiplier without Overlapping Bits, and Its 64x64 Bit Implementation.
Proceedings of the 7th Asia and South Pacific Design Automation Conference (ASP-DAC 2002), 2002

2000
An Adder Using Charge Sharing and its Application in DRAMs.
Proceedings of the IEEE International Conference On Computer Design: VLSI In Computers & Processors, 2000


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