25.4 A 20nm 6GB Function-In-Memory DRAM, Based on HBM2 with a 1.2TFLOPS Programmable Computing Unit Using Bank-Level Parallelism, for Machine Learning Applications.

[BibT_eX]

[DOI]

Young-Cheon Kwon

Suk Han Lee

Proceedings of the IEEE International Solid-State Circuits Conference, 2021

Aquabolt-XL: Samsung HBM2-PIM with in-memory processing for ML accelerators and beyond.

[BibT_eX]

[DOI]

Proceedings of the IEEE Hot Chips 33 Symposium, 2021

2019

Enforcing Last-Level Cache Partitioning through Memory Virtual Channels.

[BibT_eX]

[DOI]

Proceedings of the 28th International Conference on Parallel Architectures and Compilation Techniques, 2019

2018

Leveraging Power-Performance Relationship of Energy-Efficient Modern DRAM Devices.

[BibT_eX]

[DOI]

IEEE Access, 2018

2017

Selective DRAM cache bypassing for improving bandwidth on DRAM/NVM hybrid main memory systems.

[BibT_eX]

[DOI]

IEICE Electron. Express, 2017

SALAD: Achieving Symmetric Access Latency with Asymmetric DRAM Architecture.

[BibT_eX]

[DOI]

IEEE Comput. Archit. Lett., 2017

Understanding power-performance relationship of energy-efficient modern DRAM devices.

[BibT_eX]

[DOI]

Proceedings of the 2017 IEEE International Symposium on Workload Characterization, 2017

SOUP-N-SALAD: Allocation-Oblivious Access Latency Reduction with Asymmetric DRAM Microarchitectures.

[BibT_eX]

[DOI]

Proceedings of the 2017 IEEE International Symposium on High Performance Computer Architecture, 2017

2013

Reducing memory access latency with asymmetric DRAM bank organizations.

[BibT_eX]

[DOI]

Proceedings of the 40th Annual International Symposium on Computer Architecture, 2013

Yuhwan Ro

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