Hyunsung Shin

Orcid: 0000-0001-8104-3368

According to our database¹, Hyunsung Shin authored at least 8 papers between 2017 and 2024.

Collaborative distances:

Dijkstra number² of four.
Erdős number³ of four.

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2024

13.2 A 32Gb 8.0Gb/s/pin DDR5 SDRAM with a Symmetric-Mosaic Architecture in a 5<sup>th</sup>-Generation 10nm DRAM Process.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Solid-State Circuits Conference, 2024

2021

25.4 A 20nm 6GB Function-In-Memory DRAM, Based on HBM2 with a 1.2TFLOPS Programmable Computing Unit Using Bank-Level Parallelism, for Machine Learning Applications.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Solid-State Circuits Conference, 2021

Hardware Architecture and Software Stack for PIM Based on Commercial DRAM Technology : Industrial Product.

[BibT_eX]

[DOI]

Proceedings of the 48th ACM/IEEE Annual International Symposium on Computer Architecture, 2021

Aquabolt-XL: Samsung HBM2-PIM with in-memory processing for ML accelerators and beyond.

[BibT_eX]

[DOI]

Proceedings of the IEEE Hot Chips 33 Symposium, 2021

2020

McDRAM v2: In-Dynamic Random Access Memory Systolic Array Accelerator to Address the Large Model Problem in Deep Neural Networks on the Edge.

[BibT_eX]

[DOI]

IEEE Access, 2020

2018

McDRAM: Low Latency and Energy-Efficient Matrix Computations in DRAM.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

2017

Main Memory in HPC: Do We Need More or Could We Live with Less?

[BibT_eX]

[DOI]

ACM Trans. Archit. Code Optim., 2017

Defect Analysis and Cost-Effective Resilience Architecture for Future DRAM Devices.

[BibT_eX]

[DOI]

Proceedings of the 2017 IEEE International Symposium on High Performance Computer Architecture, 2017

Hyunsung Shin

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