Hao Zhang

Orcid: 0000-0003-3027-0485

Affiliations:
  • University of Saskatchewan, Department of Electrical and Computer Engineering, SK, Canada


According to our database1, Hao Zhang authored at least 19 papers between 2016 and 2024.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

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Bibliography

2024
Decoder Reduction Approximation Scheme for Booth Multipliers.
IEEE Trans. Computers, March, 2024

2023
Efficient Approximate Posit Multipliers for Deep Learning Computation.
IEEE J. Emerg. Sel. Topics Circuits Syst., March, 2023

Construction of Hardware Course Group in New Engineering Computer Specialty Facing Complex Engineering Problems.
Proceedings of the ACM Turing Award Celebration Conference - China 2023, 2023

2022
Variable-Precision Approximate Floating-Point Multiplier for Efficient Deep Learning Computation.
IEEE Trans. Circuits Syst. II Express Briefs, 2022

2021
A Real-Time Architecture for Pruning the Effectual Computations in Deep Neural Networks.
IEEE Trans. Circuits Syst. I Regul. Pap., 2021

Energy efficient spiking neural network processing using approximate arithmetic units and variable precision weights.
J. Parallel Distributed Comput., 2021

Efficient Multiple-Precision Posit Multiplier.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

2020
Design of Power Efficient Posit Multiplier.
IEEE Trans. Circuits Syst. II Express Briefs, 2020

New Flexible Multiple-Precision Multiply-Accumulate Unit for Deep Neural Network Training and Inference.
IEEE Trans. Computers, 2020

Novel convolutional neural network architecture for improved pulmonary nodule classification on computed tomography.
Multidimens. Syst. Signal Process., 2020

2019
Efficient Multiple-Precision Floating-Point Fused Multiply-Add with Mixed-Precision Support.
IEEE Trans. Computers, 2019

Efficient spiking neural network training and inference with reduced precision memory and computing.
IET Comput. Digit. Tech., 2019

Efficient Posit Multiply-Accumulate Unit Generator for Deep Learning Applications.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

Improved Hybrid Memory Cube for Weight-Sharing Deep Convolutional Neural Networks.
Proceedings of the IEEE International Conference on Artificial Intelligence Circuits and Systems, 2019

2018
High performance and energy efficient single-precision and double-precision merged floating-point adder on FPGA.
IET Comput. Digit. Tech., 2018

Retinal blood vessel segmentation using fully convolutional network with transfer learning.
Comput. Medical Imaging Graph., 2018

Efficient Fixed/Floating-Point Merged Mixed-Precision Multiply-Accumulate Unit for Deep Learning Processors.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

2017
Area- and power-efficient iterative single/double-precision merged floating-point multiplier on FPGA.
IET Comput. Digit. Tech., 2017

2016
Decimal floating-point fused multiply-add with redundant internal encodings.
IET Comput. Digit. Tech., 2016


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