Haoyun Jiang

According to our database1, Haoyun Jiang authored at least 19 papers between 2017 and 2023.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Links

On csauthors.net:

Bibliography

2023
A 2.85-mm<sup>2</sup> Wideband RF Transceiver in 40-nm CMOS for IoT Micro-Hub Applications.
IEEE Trans. Circuits Syst. I Regul. Pap., October, 2023

UniBrain: Universal Brain MRI Diagnosis with Hierarchical Knowledge-enhanced Pre-training.
CoRR, 2023

An All-Digital Outphasing Transmitter IC for Ka-Band Bit-to-RF Concurrent Multi-Beam DBF Array.
Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023

2022
A 24 GHz Self-Calibrated All-Digital FMCW Synthesizer With 0.01% RMS Frequency Error Under 3.2 GHz Chirp Bandwidth and 320 MHz/µs Chirp Slope.
IEEE J. Solid State Circuits, 2022

2021
32.5 A 24GHz Self-Calibrated ADPLL-Based FMCW Synthesizer with 0.01% rms Frequency Error Under 3.2GHz Chirp Bandwidth and 320MHz/μs Slope.
Proceedings of the IEEE International Solid-State Circuits Conference, 2021

Research on Interface Rate Adaptation Method Based on FPGA.
Proceedings of the 21st International Conference on Communication Technology, 2021

A 2.85mm<sup>2</sup> RF Transceiver in 40nm CMOS for IoT Micro-Hub Applications.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2021

2020
A 12-GHz Calibration-Free All-Digital PLL for FMCW Signal Generation With 78 MHz/μs Chirp Slope and High Chirp Linearity.
IEEE Trans. Circuits Syst., 2020

A 0.5-V 3.69-nW Complementary Source-Follower-C Based Low-Pass Filter for Wearable Biomedical Applications.
IEEE Trans. Circuits Syst., 2020

2019
A 28 GHz 8-Bit Calibration-Free LO-Path Phase Shifter using Transformer-Based Vector Summing Topology in 40 nm CMOS.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

A 0.5-V Ultra-Low-Power Low-Pass Filter with a Bulk-Feedback Technique.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

A Calibration-Free Fractional-N ADPLL using Retiming Architecture and a 9-bit 0.3ps-INL Phase Interpolator.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

A 12-GHz All-Digital Calibration-Free FMCW Signal Generator Based on a Retiming Fractional Frequency Divider.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2019

2018
A 2.4-mW interference-resilient receiver front end with series N-path filter-based balun for body channel communication.
Int. J. Circuit Theory Appl., 2018

A Digital Phase Noise Cancelling Scheme for Ring Oscillator-based Fractional-N ADPLL.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

A Low Power SAW-less 2.4-GHz Receiver with an LC Matched Series N-path Filter.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

A 12-bit 2.5 GHz 0.37ps-Peak-INL Digital-to-Time Converter with Parasitic-Insensitive Charge-Based Phase Interpolator.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

A 43.2 μW 2.4 GHz 64-QAM Pseudo-Backscatter Modulator Based on Integrated Directional Coupler.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

2017
An 89 μW MICS/ISM band receiver for ultra-low-power applications.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017


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