Xiucheng Hao
Orcid: 0000-0003-4602-5118Affiliations:
- Peking University, Beijing, China
According to our database1,
Xiucheng Hao
authored at least 11 papers
between 2016 and 2020.
Collaborative distances:
Collaborative distances:
Timeline
Legend:
Book In proceedings Article PhD thesis Dataset OtherLinks
Online presence:
-
on orcid.org
On csauthors.net:
Bibliography
2020
An 81-99 GHz Tripler with Fundamental Cancellation and 3rd Harmonic Enhancement Technique in 40-nm CMOS.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020
2019
A 2.9 GHz Variable Inductor-Based DCO With 1.3 kHz Frequency Resolution for FMCW Radar Applications.
IEEE Trans. Circuits Syst. II Express Briefs, 2019
A 28 GHz 8-Bit Calibration-Free LO-Path Phase Shifter using Transformer-Based Vector Summing Topology in 40 nm CMOS.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019
A Calibration-Free Fractional-N ADPLL using Retiming Architecture and a 9-bit 0.3ps-INL Phase Interpolator.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019
2018
A 2.4-mW interference-resilient receiver front end with series N-path filter-based balun for body channel communication.
Int. J. Circuit Theory Appl., 2018
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
A 12-bit 2.5 GHz 0.37ps-Peak-INL Digital-to-Time Converter with Parasitic-Insensitive Charge-Based Phase Interpolator.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
A 43.2 μW 2.4 GHz 64-QAM Pseudo-Backscatter Modulator Based on Integrated Directional Coupler.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
2017
IEICE Electron. Express, 2017
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017
2016
A 93.7% peak efficiency DC-DC buck converter with all-pass network based passive level shifter in 55 nm CMOS.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016