Harald Devos

According to our database1, Harald Devos authored at least 17 papers between 2003 and 2011.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2011
Constructing Application-Specific Memory Hierarchies on FPGAs.
Trans. HiPEAC, 2011

2010
Automatic tool flow for shift-register-LUT reconfiguration: making run-time reconfiguration fast and easy (abstract only).
Proceedings of the ACM/SIGDA 18th International Symposium on Field Programmable Gate Arrays, 2010

A Parallel for Loop Memory Template for a High Level Synthesis Compiler.
Proceedings of the 13th Euromicro Conference on Digital System Design, 2010

Towards a Tighter Integration of Generated and Custom-Made Hardware.
Proceedings of the Reconfigurable Computing: Architectures, 2010

2009
Applying Parameterizable Dynamic Configurations to Sequence Alignment.
Proceedings of the Parallel Computing: From Multicores and GPU's to Petascale, 2009

Optimizing the FPGA Memory Design for a Sobel Edge Detector.
Proceedings of the 2009 International Conference on Engineering of Reconfigurable Systems & Algorithms, 2009

2008
Loop Transformations to Reduce the Dynamic FPGA Recon?guration Overhead.
Proceedings of the ReConFig'08: 2008 International Conference on Reconfigurable Computing and FPGAs, 2008

Embedding Smart Buffers for Window Operations in a Stream-Oriented C-to-VHDL Compiler.
Proceedings of the 4th IEEE International Symposium on Electronic Design, 2008

2007
Scalable, Wavelet-Based Video: From Server to Hardware-Accelerated Client.
IEEE Trans. Multimedia, 2007

Finding and Applying Loop Transformations for Generating Optimized FPGA Implementations.
Trans. HiPEAC, 2007

FPGA Design Methodology for a Wavelet-Based Scalable Video Decoder.
Proceedings of the Embedded Computer Systems: Architectures, 2007

The Energy Scalability of Wavelet-Based, Scalable Video Decoding.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2007

Energy Scalability and the RESUME Scalable Video Codec.
Proceedings of the Power-aware Computing Systems, 21.01. - 26.01.2007, 2007

07041 Working Group - Towards Interfaces for Integrated Performance and Power Analysis and Simulation.
Proceedings of the Power-aware Computing Systems, 21.01. - 26.01.2007, 2007

2005
A Hardware-Friendly Wavelet Entropy Codec for Scalable Video.
Proceedings of the 2005 Design, 2005

2004
Reconfigurable Hardware for a Scalable Wavelet Video Decoder and Its Performance Requirements.
Proceedings of the Computer Systems: Architectures, 2004

2003
Hardware implementation of an EAN-13 bar code decoder.
Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003


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