Jan M. Van Campenhout

Orcid: 0000-0002-5910-1442

According to our database1, Jan M. Van Campenhout authored at least 75 papers between 1977 and 2016.

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Bibliography

2016
A graph-theoretic implementation of the Rabo-de-Bacalhau transformation grammar.
Artif. Intell. Eng. Des. Anal. Manuf., 2016

Optical interconnect with densely integrated plasmonic modulator and germanium photodetector arrays.
Proceedings of the Optical Fiber Communications Conference and Exhibition, 2016

2015
Toward a visual approach in the exploration of shape grammars.
Artif. Intell. Eng. Des. Anal. Manuf., 2015

2011
Constructing Application-Specific Memory Hierarchies on FPGAs.
Trans. High Perform. Embed. Archit. Compil., 2011

Three-dimensional information exchange over the semantic web for the domain of architecture, engineering, and construction.
Artif. Intell. Eng. Des. Anal. Manuf., 2011

2010
Interoperability for the Design and Construction Industry through Semantic Web Technology.
Proceedings of the Semantic Multimedia, 2010

2009
Accelerating Event-Driven Simulation of Spiking Neurons with Multiple Synaptic Time Constants.
Neural Comput., 2009

Pruning and regularization in reservoir computing.
Neurocomputing, 2009

Using method interception for hardware/software co-development.
Des. Autom. Embed. Syst., 2009

Low-Power Reconfigurable Network Architecture for On-Chip Photonic Interconnects.
Proceedings of the 17th IEEE Symposium on High Performance Interconnects, 2009

2008
Predicting the performance of reconfigurable optical interconnects in distributed shared-memory systems.
Photonic Netw. Commun., 2008

Compact hardware liquid state machines on FPGA for real-time speech recognition.
Neural Networks, 2008

Rent's rule and parallel programs: characterizing network traffic behavior.
Proceedings of the Tenth International Workshop on System-Level Interconnect Prediction (SLIP 2008), 2008

Photonic Reservoir Computing with Coupled Semiconductor Optical Amplifiers.
Proceedings of the Optical Super Computing, First International Workshop, 2008

Pruning and Regularisation in Reservoir Computing: a First Insight.
Proceedings of the 16th European Symposium on Artificial Neural Networks, 2008

2007
Systematic Simulation-Based Predictive Synthesis of Integrated Optical Interconnect.
IEEE Trans. Very Large Scale Integr. Syst., 2007

Finding and Applying Loop Transformations for Generating Optimized FPGA Implementations.
Trans. High Perform. Embed. Archit. Compil., 2007

Generative Modeling of Autonomous Robots and their Environments using Reservoir Computing.
Neural Process. Lett., 2007

Predicting reconfigurable interconnect performance in distributed shared-memory systems.
Integr., 2007

Linking non-binned spike train kernels to several existing spike train metrics.
Neurocomputing, 2007

Synthetic traffic generation as a tool for dynamic interconnect evaluation.
Proceedings of the Ninth International Workshop on System-Level Interconnect Prediction (SLIP 2007), 2007

Compact hardware for real-time speech recognition using a Liquid State Machine.
Proceedings of the International Joint Conference on Neural Networks, 2007

The Introduction of Time-Scales in Reservoir Computing, Applied to Isolated Digits Recognition.
Proceedings of the Artificial Neural Networks, 2007

An overview of reservoir computing: theory, applications and implementations.
Proceedings of the 15th European Symposium on Artificial Neural Networks, 2007

2006
A simple on-chip repetitive sampling setup for the quantification of substrate noise.
IEEE J. Solid State Circuits, 2006

Congestion modeling for reconfigurable inter-processor networks.
Proceedings of the Eigth International Workshop on System-Level Interconnect Prediction (SLIP 2006), 2006

Reconfigurable Interconnects in DSM Systems: A Focus on Context Switch Behavior.
Proceedings of the Frontiers of High Performance Computing and Networking, 2006

Backpropagation for Population-Temporal Coded Spiking Neural Networks.
Proceedings of the International Joint Conference on Neural Networks, 2006

Parallel hardware implementation of a broad class of spiking neurons using serial arithmetic.
Proceedings of the 14th European Symposium on Artificial Neural Networks, 2006

2005
Band-edge lasing in gold-clad photonic-crystal membranes.
IEEE J. Sel. Areas Commun., 2005

Isolated word recognition with the <i>Liquid State Machine</i>: a case study.
Inf. Process. Lett., 2005

Prediction model for evaluation of reconfigurable interconnects in distributed shared-memory systems.
Proceedings of the Seventh International Workshop on System-Level Interconnect Prediction (SLIP 2005), 2005

Traffic Temporal Analysis for Reconfigurable Interconnects in Shared-Memory Systems.
Proceedings of the 19th International Parallel and Distributed Processing Symposium (IPDPS 2005), 2005

2004
Toward the accurate prediction of placement wire length distributions in VLSI circuits.
IEEE Trans. Very Large Scale Integr. Syst., 2004

2003
A comparison of various terminal-gate relationships for interconnect prediction in VLSI circuits.
IEEE Trans. Very Large Scale Integr. Syst., 2003

Fast estimation of the partitioning rent characteristic using a recursive partitioning model.
Proceedings of the 5th International Workshop on System-Level Interconnect Prediction (SLIP 2003), 2003

2002
A probabilistic approach to clock cycle prediction.
Proceedings of the 8th ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems, 2002

Getting more out of Donath's hierarchical model for interconnect prediction.
Proceedings of the Fourth IEEE/ACM International Workshop on System-Level Interconnect Prediction (SLIP 2002), 2002

<i>AQUASUN</i>: adaptive window query processing in <i>CAD</i> applications for physical design and verification.
Proceedings of the 12th ACM Great Lakes Symposium on VLSI 2002, 2002

2001
A stochastic model for the interconnection topology of digital circuits.
IEEE Trans. Very Large Scale Integr. Syst., 2001

On partitioning vs. placement rent properties.
Proceedings of the Third IEEE/ACM International Workshop on System-Level Interconnect Prediction (SLIP 2001), March 31, 2001

On rent's rule for rectangular regions.
Proceedings of the Third IEEE/ACM International Workshop on System-Level Interconnect Prediction (SLIP 2001), March 31, 2001

2000
Generating synthetic benchmark circuits for evaluating CAD tools.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000

On synthetic benchmark generation methods.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

1999
Accurate Interconnection Length Estimations for Predictions Early in the Design Cycle.
VLSI Design, 1999

Exploitable levels of ILP in future processors.
J. Syst. Archit., 1999

A fast, cache-aware algorithm for the calculation of radiological paths exploiting subword parallelism.
J. Syst. Archit., 1999

Generating new benchmark designs using a multi-terminal net model.
Integr., 1999

Towards synthetic benchmark circuits for evaluating timing-driven CAD tools.
Proceedings of the 1999 International Symposium on Physical Design, 1999

Investigating the Implementation of a Block Structured Architecture in an Early Design Stage.
Proceedings of the 25th EUROMICRO '99 Conference, 1999

1998
On the Use of Subword Parallelism in Medical Image Processing.
Parallel Comput., 1998

ESCAPE: environment for the simulation of computer architectures for the purpose of education.
Proceedings of the 1998 workshop on Computer architecture education, 1998

A Quantitative Study of the Benefits of Area-I/O in FPGAs.
Proceedings of the 8th Great Lakes Symposium on VLSI (GLS-VLSI '98), 1998

GART: A New, Flexible Placement and Routing Tool for Research on FPGA Architectures (Abstract).
Proceedings of the 1998 ACM/SIGDA Sixth International Symposium on Field Programmable Gate Arrays, 1998

1997
A quantitative analysis of the benefits of the use of area-I/O pads in FPGAs.
Microprocess. Microsystems, 1997

1996
Ultrasonic Perception: A Tri-aural Sensor Array for Mobile Robots using A Competition Neural Network Approach.
Proceedings of the Industrial and Engineering Applications of Artificial Intelligence and Expert Systems, 1996

An Accurate Interconnection Length Estimation for Computer Logic.
Proceedings of the 6th Great Lakes Symposium on VLSI (GLS-VLSI '96), 1996

Hierarchical Test Generation with Built-In Fault Diagnosis.
Proceedings of the 5th Asian Test Symposium (ATS '96), 1996

1994
A New Trace And Replay System For Shared Memory Programs Based On Lamport Clocks.
Proceedings of the Second Euromicro Workshop on Parallel and Distributed Processing, 1994

A Transputer-based Neural Network To Determine Object Positions From Tri-aural Ultrasonic Sensor Data.
Proceedings of the Second Euromicro Workshop on Parallel and Distributed Processing, 1994

An Optoelectronic 3-D Field Programmable Gate Array.
Proceedings of the Field-Programmable Logic, 1994

Execution Replay with Compact Logs for Shared-Memory Programs.
Proceedings of the Applications in Parallel and Distributed Computing, 1994

1993
A high-resolution sensor based on tri-aural perception.
IEEE Trans. Robotics Autom., 1993

A correlation coprocessor for accurate real-time ultrasonic ranging of multiple objects using the transputer.
Microprocess. Microsystems, 1993

PRIP - A Parallel Raster Image Processor.
Comput. Graph. Forum, 1993

Some low-level issues in the implementation of a shared blackboard.
Proceedings of the 1993 Euromicro Workshop on Parallel and Distributed Processing, 1993

Tri-Aural Perception on a Mobile Robot.
Proceedings of the 1993 IEEE International Conference on Robotics and Automation, 1993

1992
Accurate ranging of multiple objects using ultrasonic sensors.
Proceedings of the 1992 IEEE International Conference on Robotics and Automation, 1992

1990
Interpretation and instruction path coprocessing.
Computer systems, MIT Press, ISBN: 978-0-262-04107-2, 1990

1987
Language coprocessor to support the interpretation of MODULA-2 programs.
Microprocess. Microsystems, 1987

1982
36 Topics in measurement selection.
Proceedings of the Classification, Pattern Recognition and Reduction of Dimensionality, 1982

1981
Maximum entropy and conditional probability.
IEEE Trans. Inf. Theory, 1981

1978
On the Peaking of the Hughes Mean Recognition Accuracy: The Resolution of an Apparent Paradox.
IEEE Trans. Syst. Man Cybern., 1978

A Stochastic Model for Closed-Loop Preemptive Microprocessor I/O Organizations.
IEEE Trans. Computers, 1978

1977
On the Possible Orderings in the Measurement Selection Problem.
IEEE Trans. Syst. Man Cybern., 1977


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