Karel Bruneel

According to our database1, Karel Bruneel authored at least 33 papers between 2007 and 2015.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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PhD thesis 
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Bibliography

2015
Identification of Dynamic Circuit Specialization Opportunities in RTL Code.
ACM Trans. Reconfigurable Technol. Syst., 2015

TCONMAP: Technology Mapping for Parameterised FPGA Configurations.
ACM Trans. Design Autom. Electr. Syst., 2015

FASTER: Facilitating Analysis and Synthesis Technologies for Effective Reconfiguration.
Microprocess. Microsystems, 2015

Enabling FPGA routing configuration sharing in dynamic partial reconfiguration.
Des. Autom. Embed. Syst., 2015

2014
TPaR: Place and Route Tools for the Dynamic Reconfiguration of the FPGA's Interconnect Network.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014

2013
How to efficiently implement dynamic circuit specialization systems.
ACM Trans. Design Autom. Electr. Syst., 2013

A novel tool flow for increased routing configuration similarity in multi-mode circuits.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2013

A connection-based router for FPGAs.
Proceedings of the 2013 International Conference on Field-Programmable Technology, 2013

Efficient implementation of Virtual Coarse Grained Reconfigurable Arrays on FPGAS.
Proceedings of the 23rd International Conference on Field programmable Logic and Applications, 2013

Staticroute: A novel router for the Dynamic Partial Reconfiguration of FPGAS.
Proceedings of the 23rd International Conference on Field programmable Logic and Applications, 2013

An automatic tool flow for the combined implementation of multi-mode circuits.
Proceedings of the Design, Automation and Test in Europe, 2013

2012
Dynamic Circuit Specialisation for Key-Based Encryption Algorithms and DNA Alignment.
Int. J. Reconfigurable Comput., 2012

Maximizing the reuse of routing resources in a reconfiguration-aware connection router.
Proceedings of the 22nd International Conference on Field Programmable Logic and Applications (FPL), 2012

Mapping logic to reconfigurable FPGA routing.
Proceedings of the 22nd International Conference on Field Programmable Logic and Applications (FPL), 2012

Automatically exploiting regularity in applications to reduce reconfiguration memory requirements.
Proceedings of the 22nd International Conference on Field Programmable Logic and Applications (FPL), 2012

FASTER: Facilitating Analysis and Synthesis Technologies for Effective Reconfiguration.
Proceedings of the 15th Euromicro Conference on Digital System Design, 2012

A Connection Router for the Dynamic Reconfiguration of FPGAs.
Proceedings of the Reconfigurable Computing: Architectures, Tools and Applications, 2012

Automating Reconfiguration Chain Generation for SRL-Based Run-Time Reconfiguration.
Proceedings of the Reconfigurable Computing: Architectures, Tools and Applications, 2012

2011
Dynamic data folding with parameterizable FPGA configurations.
ACM Trans. Design Autom. Electr. Syst., 2011

RecoNoC: A reconfigurable network-on-chip.
Proceedings of the 6th International Workshop on Reconfigurable Communication-centric Systems-on-Chip, 2011

A Dynamically Reconfigurable Pattern Matcher for Regular Expressions on FPGA.
Proceedings of the Applications, Tools and Techniques on the Road to Exascale Computing, Proceedings of the conference ParCo 2011, 31 August, 2011

Memory-Efficient and Fast Run-Time Reconfiguration of Regularly Structured Designs.
Proceedings of the International Conference on Field Programmable Logic and Applications, 2011

2010
Run-Time Reconfiguration for Automatic Hardware/Software Partitioning.
Proceedings of the ReConFig'10: 2010 International Conference on Reconfigurable Computing and FPGAs, 2010

Efficiently Generating FPGA Configurations through a Stack Machine.
Proceedings of the International Conference on Field Programmable Logic and Applications, 2010

Automatic tool flow for shift-register-LUT reconfiguration: making run-time reconfiguration fast and easy (abstract only).
Proceedings of the ACM/SIGDA 18th International Symposium on Field Programmable Gate Arrays, 2010

TROUTE: A Reconfigurability-Aware FPGA Router.
Proceedings of the Reconfigurable Computing: Architectures, 2010

2009
Applying Parameterizable Dynamic Configurations to Sequence Alignment.
Proceedings of the Parallel Computing: From Multicores and GPU's to Petascale, 2009

Towards a more efficient run-time FPGA configuration generation.
Proceedings of the Parallel Computing: From Multicores and GPU's to Petascale, 2009

Automatically mapping applications to a self-reconfiguring platform.
Proceedings of the Design, Automation and Test in Europe, 2009

2008
Loop Transformations to Reduce the Dynamic FPGA Recon?guration Overhead.
Proceedings of the ReConFig'08: 2008 International Conference on Reconfigurable Computing and FPGAs, 2008

Reconfigurability-Aware Structural Mapping for LUT-Based FPGAs.
Proceedings of the ReConFig'08: 2008 International Conference on Reconfigurable Computing and FPGAs, 2008

Automatic generation of run-time parameterizable configurations.
Proceedings of the FPL 2008, 2008

2007
A Method for Fast Hardware Specialization at run-time.
Proceedings of the FPL 2007, 2007


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