Hari Addepalli

According to our database, Hari Addepalli authored at least 4 papers between 2022 and 2024.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2024

Delay Monitoring Under Different PVT Corners for Test and Functional Operation.

Hari Addepalli, Jiezhong Wu, Nilanjan Mukherjee, Irith Pomeranz, Janusz Rajski

Proceedings of the IEEE International Test Conference, 2024

Generating Storage-Aware Test Sets Targeting Several Fault Models.

Hari Addepalli, Irith Pomeranz, M. Enamul Amyeen, Suriyaprakash Natarajan, Arani Sinha, Srikanth Venkataraman

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2024

2022

Algorithms for the Selection of Applied Tests when a Stored Test Produces Many Applied Tests.

Hari Addepalli, Irith Pomeranz

Proceedings of the GLSVLSI '22: Great Lakes Symposium on VLSI 2022, Irvine CA USA, June 6, 2022

Using Fault Detection Tests to Produce Diagnostic Tests Targeting Large Sets of Candidate Faults.

Hari Addepalli, Irith Pomeranz, M. Enamul Amyeen, Suriyaprakash Natarajan, Arani Sinha, Srikanth Venkataraman

Proceedings of the IEEE 31st Asian Test Symposium, 2022