Janusz Rajski

Justyna Zawada

Proceedings of the IEEE International Test Conference, 2018

Deterministic Stellar BIST for In-System Automotive Test.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Test Conference, 2018

DPPM Reduction Methods and New Defect Oriented Test Methods Applied to Advanced FinFET Technologies.

[BibT_eX]

[DOI]

Will Howell

Friedrich Hapke

Edward Brazil

Srikanth Venkataraman

Proceedings of the IEEE International Test Conference, 2018

Hypercompression of Test Patterns.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Test Conference, 2018

2017

Trimodal Scan-Based Test Paradigm.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2017

Embedded Deterministic Test Points.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2017

Star-EDT: Deterministic On-Chip Scheme Using Compressed Test Patterns.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017

Full-scan LBIST with capture-per-cycle hybrid test points.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Test Conference, 2017

ROM fault diagnosis for O(n<sup>2</sup>) test algorithms.

[BibT_eX]

[DOI]

Artur Pogiel

Proceedings of the 22nd IEEE European Test Symposium, 2017

2016

On New Test Points for Compact Cell-Aware Tests.

[BibT_eX]

[DOI]

IEEE Des. Test, 2016

Digital Testing of ICs for Automotive Applications.

[BibT_eX]

[DOI]

Proceedings of the 29th International Conference on VLSI Design and 15th International Conference on Embedded Systems, 2016

Test point insertion in hybrid test compression/LBIST architectures.

[BibT_eX]

[DOI]

Proceedings of the 2016 IEEE International Test Conference, 2016

Minimal area test points for deterministic patterns.

[BibT_eX]

[DOI]

Proceedings of the 2016 IEEE International Test Conference, 2016

Transistor stuck-on fault detection tests for digital CMOS circuits.

[BibT_eX]

[DOI]

Proceedings of the 21th IEEE European Test Symposium, 2016

On Test Points Enhancing Hardware Security.

[BibT_eX]

[DOI]

Proceedings of the 25th IEEE Asian Test Symposium, 2016

2015

Low-Power Programmable PRPG With Test Compression Capabilities.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2015

Scan Test Bandwidth Management for Ultralarge-Scale System-on-Chip Architectures.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2015

Isometric Test Data Compression.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015

Innovative practices session 11C: Advanced scan methodologies [3 presentations].

[BibT_eX]

[DOI]

Proceedings of the 33rd IEEE VLSI Test Symposium, 2015

Using Boolean Tests to Improve Detection of Transistor Stuck-Open Faults in CMOS Digital Logic Circuits.

[BibT_eX]

[DOI]

Proceedings of the 28th International Conference on VLSI Design, 2015

Clock-domain-aware test for improving pattern compression.

[BibT_eX]

[DOI]

Proceedings of the VLSI Design, Automation and Test, 2015

Hybrid Hierarchical and Modular Tests for SoC Designs.

[BibT_eX]

[DOI]

Proceedings of the 24th IEEE North Atlantic Test Workshop, 2015

A deterministic BIST scheme based on EDT-compressed test patterns.

[BibT_eX]

[DOI]

Proceedings of the 2015 IEEE International Test Conference, 2015

Embedded deterministic test points for compact cell-aware tests.

[BibT_eX]

[DOI]

Proceedings of the 2015 IEEE International Test Conference, 2015

Design for low test pattern counts.

[BibT_eX]

[DOI]

Proceedings of the 52nd Annual Design Automation Conference, 2015

TestExpress - New Time-Effective Scan-Based Deterministic Test Paradigm.

[BibT_eX]

[DOI]

Proceedings of the 24th IEEE Asian Test Symposium, 2015

On Improving Transition Test Set Quality to Detect CMOS Transistor Stuck-Open Faults.

[BibT_eX]

[DOI]

Wu-Tung Cheng

Proceedings of the 24th IEEE Asian Test Symposium, 2015

2014

Erratum to "Test Time Reduction in EDT Bandwidth Management for SoC Designs".

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014

Cell-Aware Test.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014

Special session 8B - Panel: In-field testing of SoC devices: Which solutions by which players?

[BibT_eX]

[DOI]

Proceedings of the 32nd IEEE VLSI Test Symposium, 2014

Test Compression Improvement with EDT Channel Sharing in SoC Designs.

[BibT_eX]

[DOI]

Proceedings of the IEEE 23rd North Atlantic Test Workshop, 2014

Isometric test compression with low toggling activity.

[BibT_eX]

[DOI]

Proceedings of the 2014 International Test Conference, 2014

Using dynamic shift to reduce test data volume in high-compression designs.

[BibT_eX]

[DOI]

Proceedings of the 19th IEEE European Test Symposium, 2014

Cell-aware experiences in a high-quality automotive test suite.

[BibT_eX]

[DOI]

Proceedings of the 19th IEEE European Test Symposium, 2014

Quality assurance in memory built-in self-test tools.

[BibT_eX]

[DOI]

Proceedings of the 17th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2014

On Using Implied Values in EDT-based Test Compression.

[BibT_eX]

[DOI]

Proceedings of the 51st Annual Design Automation Conference 2014, 2014

High-Speed Serial Embedded Deterministic Test for System-on-Chip Designs.

[BibT_eX]

[DOI]

Proceedings of the 23rd IEEE Asian Test Symposium, 2014

Low Power Test Compression with Programmable Broadcast-Based Control.

[BibT_eX]

[DOI]

Proceedings of the 23rd IEEE Asian Test Symposium, 2014

2013

Test Time Reduction in EDT Bandwidth Management for SoC Designs.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013

On Deploying Scan Chains for Data Storage in Test Compression Environment.

[BibT_eX]

[DOI]

IEEE Des. Test, 2013

Embedded tutorials: Embedded tutorial 1: Cell-aware test-from gates to transistors.

[BibT_eX]

[DOI]

Proceedings of the 21st IEEE/IFIP International Conference on VLSI and System-on-Chip, 2013

Fault diagnosis of TSV-based interconnects in 3-D stacked designs.

[BibT_eX]

[DOI]

Proceedings of the 2013 IEEE International Test Conference, 2013

On the generation of compact test sets.

[BibT_eX]

[DOI]

Proceedings of the 2013 IEEE International Test Conference, 2013

EDT bandwidth management - Practical scenarios for large SoC designs.

[BibT_eX]

[DOI]

Proceedings of the 2013 IEEE International Test Conference, 2013

New test compression scheme based on low power BIST.

[BibT_eX]

[DOI]

Proceedings of the 18th IEEE European Test Symposium, 2013

On the Generation of Compact Deterministic Test Sets for BIST Ready Designs.

[BibT_eX]

[DOI]

Proceedings of the 22nd Asian Test Symposium, 2013

2012

EDT Bandwidth Management in SoC Designs.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012

Test generator with preselected toggling for low power built-in self-test.

[BibT_eX]

[DOI]

Proceedings of the 30th IEEE VLSI Test Symposium, 2012

Low power programmable PRPG with enhanced fault coverage gradient.

[BibT_eX]

[DOI]

Proceedings of the 2012 IEEE International Test Conference, 2012

Cell-aware Production test results from a 32-nm notebook processor.

[BibT_eX]

[DOI]

Proceedings of the 2012 IEEE International Test Conference, 2012

Low power test application with selective compaction in VLSI designs.

[BibT_eX]

[DOI]

Dariusz Czysz

Proceedings of the 2012 IEEE International Test Conference, 2012

Bandwidth-aware test compression logic for SoC designs.

[BibT_eX]

[DOI]

Proceedings of the 17th IEEE European Test Symposium, 2012

On Utilizing Test Cube Properties to Reduce Test Data Volume Further.

[BibT_eX]

[DOI]

Proceedings of the 21st IEEE Asian Test Symposium, 2012

2011

BIST-Based Fault Diagnosis for Read-Only Memories.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011

Deterministic Clustering of Incompatible Test Cubes for Higher Power-Aware EDT Compression.

[BibT_eX]

[DOI]

Przemyslaw Szczerbicki

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011

Fault Diagnosis with Orthogonal Compactors in Scan-Based Designs.

[BibT_eX]

[DOI]

J. Electron. Test., 2011

Ring Generator: An Ultimate Linear Feedback Shift Register.

[BibT_eX]

[DOI]

Computer, 2011

Low power compression utilizing clock-gating.

[BibT_eX]

[DOI]

Elham K. Moghaddam

Proceedings of the 2011 IEEE International Test Conference, 2011

EDT channel bandwidth management in SoC designs with pattern-independent test access mechanism.

[BibT_eX]

[DOI]

Proceedings of the 2011 IEEE International Test Conference, 2011

Cell-aware analysis for small-delay effects and production test results from different fault models.

[BibT_eX]

[DOI]

Proceedings of the 2011 IEEE International Test Conference, 2011

Reduced ATE Interface for High Test Data Compression.

[BibT_eX]

[DOI]

Proceedings of the 16th European Test Symposium, 2011

Fault Diagnosis in Memory BIST Environment with Non-march Tests.

[BibT_eX]

[DOI]

Proceedings of the 20th IEEE Asian Test Symposium, 2011

Low Test Data Volume Low Power At-Speed Delay Tests Using Clock-Gating.

[BibT_eX]

[DOI]

Proceedings of the 20th IEEE Asian Test Symposium, 2011

Power Aware Embedded Test.

[BibT_eX]

[DOI]

Proceedings of the 20th IEEE Asian Test Symposium, 2011

Low Power Decompressor and PRPG with Constant Value Broadcast.

[BibT_eX]

[DOI]

Proceedings of the 20th IEEE Asian Test Symposium, 2011

2010

High Volume Diagnosis in Memory BIST Based on Compressed Failure Data.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010

On Compaction Utilizing Inter and Intra-Correlation of Unknown States.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010

At-speed scan test with low switching activity.

[BibT_eX]

[DOI]

Proceedings of the 28th IEEE VLSI Test Symposium, 2010

Low capture power at-speed test in EDT environment.

[BibT_eX]

[DOI]

Proceedings of the 2011 IEEE International Test Conference, 2010

Dynamic channel allocation for higher EDT compression in SoC designs.

[BibT_eX]

[DOI]

Proceedings of the 2011 IEEE International Test Conference, 2010

Low power compression of incompatible test cubes.

[BibT_eX]

[DOI]

Przemyslaw Szczerbicki

Proceedings of the 2011 IEEE International Test Conference, 2010

Diagnosis of failing scan cells through orthogonal response compaction.

[BibT_eX]

[DOI]

Proceedings of the 15th European Test Symposium, 2010

Adaptive Low Shift Power Test Pattern Generator for Logic BIST.

[BibT_eX]

[DOI]

Proceedings of the 19th IEEE Asian Test Symposium, 2010

2009

Timing-Aware Multiple-Delay-Fault Diagnosis.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009

Low-Power Scan Operation in Test Compression Environment.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009

Highly X-Tolerant Selective Compaction of Test Responses.

[BibT_eX]

[DOI]

Proceedings of the 27th IEEE VLSI Test Symposium, 2009

Defect Aware to Power Conscious Tests - The New DFT Landscape.

[BibT_eX]

[DOI]

Proceedings of the VLSI Design 2009: Improving Productivity through Higher Abstraction, 2009

High-Speed On-Chip Event Counters for Embedded Systems.

[BibT_eX]

[DOI]

Proceedings of the VLSI Design 2009: Improving Productivity through Higher Abstraction, 2009

Fault diagnosis for embedded read-only memories.

[BibT_eX]

[DOI]

Proceedings of the 2009 IEEE International Test Conference, 2009

Compression based on deterministic vector clustering of incompatible test cubes.

[BibT_eX]

[DOI]

Proceedings of the 2009 IEEE International Test Conference, 2009

We Have Got Compression, What Next?

[BibT_eX]

[DOI]

Proceedings of the 14th IEEE European Test Symposium, 2009

A scalable method for the generation of small test sets.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2009

N-distinguishing Tests for Enhanced Defect Diagnosis.

[BibT_eX]

[DOI]

Proceedings of the Eighteentgh Asian Test Symposium, 2009

2008

X-Press: Two-Stage X-Tolerant Compactor With Programmable Selector.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008

Improving the Resolution of Single-Delay-Fault Diagnosis.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008

Low-Power Test Data Application in EDT Environment Through Decompressor Freeze.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008

High Throughput Diagnosis via Compression of Failure Data in Embedded Memory BIST.

[BibT_eX]

[DOI]

Proceedings of the 2008 IEEE International Test Conference, 2008

Test Generation for Interconnect Opens.

[BibT_eX]

[DOI]

Proceedings of the 2008 IEEE International Test Conference, 2008

Low Power Scan Shift and Capture in the EDT Environment.

[BibT_eX]

[DOI]

Proceedings of the 2008 IEEE International Test Conference, 2008

ATPG Heuristics Dependant Observation Point Insertion for Enhanced Compaction and Data Volume Reduction.

[BibT_eX]

[DOI]

Proceedings of the 23rd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2008), 2008

Test Power Reduction by Blocking Scan Cell Outputs.

[BibT_eX]

[DOI]

Proceedings of the 17th IEEE Asian Test Symposium, 2008

2007

Fault Diagnosis With Convolutional Compactors.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007

Enhancing delay fault coverage through low-power segmented scan.

[BibT_eX]

[DOI]

IET Comput. Digit. Tech., 2007

Isolation of Failing Scan Cells through Convolutional Test Response Compaction.

[BibT_eX]

[DOI]

J. Electron. Test., 2007

X-Tolerant Compactor with On-Chip Registration and Signature-Based Diagnosis.

[BibT_eX]

[DOI]

IEEE Des. Test Comput., 2007

Scan-Based Tests with Low Switching Activity.

[BibT_eX]

[DOI]

IEEE Des. Test Comput., 2007

Silicon Evaluation of Static Alternative Fault Models.

[BibT_eX]

[DOI]

Proceedings of the 25th IEEE VLSI Test Symposium (VTS 2007), 2007

Low Power Embedded Deterministic Test.

[BibT_eX]

[DOI]

Proceedings of the 25th IEEE VLSI Test Symposium (VTS 2007), 2007

Low Shift and Capture Power Scan Tests.

[BibT_eX]

[DOI]

Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007

Analyzing Volume Diagnosis Results with Statistical Learning for Yield Improvement.

[BibT_eX]

[DOI]

Proceedings of the 12th European Test Symposium, 2007

Logic Diagnosis and Yield Learning.

[BibT_eX]

[DOI]

Proceedings of the 10th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2007), 2007

New Test Data Decompressor for Low Power Applications.

[BibT_eX]

[DOI]

Proceedings of the 44th Design Automation Conference, 2007

Test Generation in the Presence of Timing Exceptions and Constraints.

[BibT_eX]

[DOI]

Proceedings of the 44th Design Automation Conference, 2007

Test Generation for Timing-Critical Transition Faults.

[BibT_eX]

[DOI]

Proceedings of the 16th Asian Test Symposium, 2007

2006

Analysis and methodology for multiple-fault diagnosis.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

High Performance Dense Ring Generators.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2006

Scan Tests with Multiple Fault Activation Cycles for Delay Faults.

[BibT_eX]

[DOI]

Proceedings of the 24th IEEE VLSI Test Symposium (VTS 2006), 30 April, 2006

Modular Compactor of Test Responses.

[BibT_eX]

[DOI]

Wojciech Rajski

Proceedings of the 24th IEEE VLSI Test Symposium (VTS 2006), 30 April, 2006

The Impacts of Untestable Defects on Transition Fault Testing.

[BibT_eX]

[DOI]

Proceedings of the 24th IEEE VLSI Test Symposium (VTS 2006), 30 April, 2006

New Procedures to Identify Redundant Stuck-At Faults and Removal of Redundant Logic.

[BibT_eX]

[DOI]

Proceedings of the 19th International Conference on VLSI Design (VLSI Design 2006), 2006

Preferred Fill: A Scalable Method to Reduce Capture Power for Scan Based Designs.

[BibT_eX]

[DOI]

Proceedings of the 2006 IEEE International Test Conference, 2006

X-Press Compactor for 1000x Reduction of Test Data.

[BibT_eX]

[DOI]

Proceedings of the 2006 IEEE International Test Conference, 2006

Timing Defect Diagnosis in Presence of Crosstalk for Nanometer Technology.

[BibT_eX]

[DOI]

Proceedings of the 2006 IEEE International Test Conference, 2006

A Rapid Yield Learning Flow Based on Production Integrated Layout-Aware Diagnosis.

[BibT_eX]

[DOI]

Proceedings of the 2006 IEEE International Test Conference, 2006

Diagnosis with Limited Failure Information.

[BibT_eX]

[DOI]

Proceedings of the 2006 IEEE International Test Conference, 2006

Delay Fault Diagnosis for Non-Robust Test.

[BibT_eX]

[DOI]

Proceedings of the 7th International Symposium on Quality of Electronic Design (ISQED 2006), 2006

Convolutional Compactors with Variable Polynomials.

[BibT_eX]

[DOI]

Artur Pogiel

Proceedings of the 11th European Test Symposium, 2006

Test response compactor with programmable selector.

[BibT_eX]

[DOI]

Proceedings of the 43rd Design Automation Conference, 2006

A test pattern ordering algorithm for diagnosis with truncated fail data.

[BibT_eX]

[DOI]

Proceedings of the 43rd Design Automation Conference, 2006

Timing-Aware ATPG for High Quality At-speed Testing of Small Delay Defects.

[BibT_eX]

[DOI]

Proceedings of the 15th Asian Test Symposium, 2006

At-Speed Testing with Timing Exceptions and Constraints-Case Studies.

[BibT_eX]

[DOI]

Proceedings of the 15th Asian Test Symposium, 2006

2005

Delay-fault diagnosis using timing information.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005

Finite memory test response compactors for embedded test applications.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005

Synthesis of X-Tolerant Convolutional Compactors.

[BibT_eX]

[DOI]

Proceedings of the 23rd IEEE VLSI Test Symposium (VTS 2005), 2005

On Efficient X-Handling Using a Selective Compaction Scheme to Achieve High Test Response Compaction Ratios.

[BibT_eX]

[DOI]

Proceedings of the 18th International Conference on VLSI Design (VLSI Design 2005), 2005

Test compression - real issues and matching solutions.

[BibT_eX]

[DOI]

Proceedings of the Proceedings 2005 IEEE International Test Conference, 2005

Diagnosis with convolutional compactors in presence of unknown states.

[BibT_eX]

[DOI]

Proceedings of the Proceedings 2005 IEEE International Test Conference, 2005

Compressed pattern diagnosis for scan chain failures.

[BibT_eX]

[DOI]

Yu Huang

Wu-Tung Cheng

Proceedings of the Proceedings 2005 IEEE International Test Conference, 2005

Convolutional compaction-driven diagnosis of scan failures.

[BibT_eX]

[DOI]

Proceedings of the 10th European Test Symposium, 2005

A unified fault model and test generation procedure for interconnect opens and bridges.

[BibT_eX]

[DOI]

Proceedings of the 10th European Test Symposium, 2005

Defect Aware Test Patterns.

[BibT_eX]

[DOI]

Proceedings of the 2005 Design, 2005

Embedded Test Technology - Brief History, Current Status, and Future Directions.

[BibT_eX]

[DOI]

Proceedings of the 14th Asian Test Symposium (ATS 2005), 2005

Propagation delay fault: a new fault model to test delay faults.

[BibT_eX]

[DOI]

Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

2004

Embedded deterministic test.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004

Ring generators - new devices for embedded test applications.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004

Planar High Performance Ring Generators.

[BibT_eX]

[DOI]

Proceedings of the 22nd IEEE VLSI Test Symposium (VTS 2004), 2004

Embedded Test for Low Cost Manufacturing.

[BibT_eX]

[DOI]

Proceedings of the 17th International Conference on VLSI Design (VLSI Design 2004), 2004

Fault Diagnosis in Designs with Convolutional Compactors.

[BibT_eX]

[DOI]

Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004

Realizing High Test Quality Goals with Smart Test Resource Usage.

[BibT_eX]

[DOI]

Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004

Affordable and Effective Screening of Delay Defects in ASICs using the Inline Resistance Fault Model.

[BibT_eX]

[DOI]

Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004

Diagnosis of Hold Time Defects.

[BibT_eX]

[DOI]

Proceedings of the 22nd IEEE International Conference on Computer Design: VLSI in Computers & Processors (ICCD 2004), 2004

Nanometer Design: What are the Requirements for Manufacturing Test?

[BibT_eX]

[DOI]

Kan Thapar

Proceedings of the 2004 Design, 2004

Compactor Independent Direct Diagnosis.

[BibT_eX]

[DOI]

Proceedings of the 13th Asian Test Symposium (ATS 2004), 2004

2003

Primitive Polynomials Over GF(2) of Degree up to 660 with Uniformly Distributed Coefficients.

[BibT_eX]

[DOI]

J. Electron. Test., 2003

Embedded Deterministic Test for Low-Cost Manufacturing.

[BibT_eX]

[DOI]

IEEE Des. Test Comput., 2003

2D Test Sequence Generators.

[BibT_eX]

[DOI]

IEEE Des. Test Comput., 2003

High-Frequency, At-Speed Scan Testing.

[BibT_eX]

[DOI]

IEEE Des. Test Comput., 2003

High Speed Ring Generators and Compactors of Test Data.

[BibT_eX]

[DOI]

Proceedings of the 21st IEEE VLSI Test Symposium (VTS 2003), 27 April, 2003

An Efficient and Effective Methodology on the Multiple Fault Diagnosis.

[BibT_eX]

[DOI]

Proceedings of the Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September, 2003

Convolutional Compaction of Test Responses.

[BibT_eX]

[DOI]

Proceedings of the Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September, 2003

Test Challenges of Nanometer Technology.

[BibT_eX]

[DOI]

Proceedings of the Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September, 2003

Industrial Experience with Adoption of EDT for Low-Cost Test without Concessions.

[BibT_eX]

[DOI]

Proceedings of the Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September, 2003

Impact of Multiple-Detect Test Patterns on Product Quality.

[BibT_eX]

[DOI]

Brady Benware

Chris Schuermyer

Sreenevasan Ranganathan

Proceedings of the Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September, 2003

Multiple Fault Diagnosis Using n-Detection Tests.

[BibT_eX]

[DOI]

Proceedings of the 21st International Conference on Computer Design (ICCD 2003), 2003

Test Data Compression and Compaction for Embedded Test of Nanometer Technology Designs.

[BibT_eX]

[DOI]

Proceedings of the 21st International Conference on Computer Design (ICCD 2003), 2003

On Compacting Test Response Data Containing Unknown Values.

[BibT_eX]

[DOI]

Proceedings of the 2003 International Conference on Computer-Aided Design, 2003

2002

Innovations in Test Automation.

[BibT_eX]

[DOI]

Proceedings of the 20th IEEE VLSI Test Symposium (VTS 2002), Without Testing It's a Gamble, 28 April, 2002

Improved Algorithms for Constructive Multi-Phase Test Point Insertion for Scan Based BIST.

[BibT_eX]

[DOI]

Nadir Z. Basturkmen

Proceedings of the 7th Asia and South Pacific Design Automation Conference (ASP-DAC 2002), 2002

Embedded Deterministic Test for Low-Cost Manufacturing Test.

[BibT_eX]

[DOI]

Proceedings of the Proceedings IEEE International Test Conference 2002, 2002

Conflict driven techniques for improving deterministic test pattern generation.

[BibT_eX]

[DOI]

Proceedings of the 2002 IEEE/ACM International Conference on Computer-aided Design, 2002

Finding a Common Fault Response for Diagnosis during Silicon Debug.

[BibT_eX]

[DOI]

Irith Pomeranz

Proceedings of the 2002 Design, 2002

2001

Testing Schemes for FIR Filter Structures.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2001

Enabling Embedded Memory Diagnosis via Test Response Compression.

[BibT_eX]

[DOI]

Proceedings of the 19th IEEE VLSI Test Symposium (VTS 2001), Test and Diagnosis in a Nanometric World, 29 April, 2001

On static test compaction and test pattern ordering for scan designs.

[BibT_eX]

[DOI]

Proceedings of the Proceedings IEEE International Test Conference 2001, Baltimore, MD, USA, 30 October, 2001

Test response compression and bitmap encoding for embedded memories in manufacturing process monitoring.

[BibT_eX]

[DOI]

Proceedings of the Proceedings IEEE International Test Conference 2001, Baltimore, MD, USA, 30 October, 2001

DFT for High-Quality Low Cost Manufacturing Test.

[BibT_eX]

[DOI]

Proceedings of the 10th Asian Test Symposium (ATS 2001), 19-21 November 2001, Kyoto, Japan, 2001

2000

Star test: the theory and its applications.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000

Automated synthesis of phase shifters for built-in self-testapplications.

[BibT_eX]

[DOI]

Nagesh Tamarapalli

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000

Cellular automata-based test pattern generators with phase shifters.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000

Linear Independence as Evaluation Criterion for Two-Dimensional Test Pattern Generators.

[BibT_eX]

[DOI]

Proceedings of the 18th IEEE VLSI Test Symposium (VTS 2000), 30 April, 2000

Improving the Proportion of At-Speed Tests in Scan BIST.

[BibT_eX]

[DOI]

Proceedings of the 2000 IEEE/ACM International Conference on Computer-Aided Design, 2000

Self-test methodology for at-speed test of crosstalk in chip interconnects.

[BibT_eX]

[DOI]

Xiaoliang Bai

Sujit Dey

Proceedings of the 37th Conference on Design Automation, 2000

1999

Diagnosis of Scan Cells in BIST Environment.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 1999

Testing of telecommunications hardware [Guest Editorial].

[BibT_eX]

[DOI]

IEEE Commun. Mag., 1999

Comparative Study of CA-based PRPGs and LFSRs with Phase Shifters.

[BibT_eX]

[DOI]

Proceedings of the 17th IEEE VLSI Test Symposium (VTS '99), 1999

Built-In Self-Test for Systems on Silicon.

[BibT_eX]

[DOI]

Sanjay Patel

Proceedings of the 12th International Conference on VLSI Design (VLSI Design 1999), 1999

STAR-ATPG: a high speed test pattern generator for large scan designs.

[BibT_eX]

[DOI]

Kuo-Hui Tsai

Tompson

Proceedings of the Proceedings IEEE International Test Conference 1999, 1999

Synthesis of pattern generators based on cellular automata with phase shifters.

[BibT_eX]

[DOI]

Proceedings of the Proceedings IEEE International Test Conference 1999, 1999

Logic BIST for large industrial designs: real issues and case studies.

[BibT_eX]

[DOI]

Proceedings of the Proceedings IEEE International Test Conference 1999, 1999

1998

Test Data Decompression for Multiple Scan Designs with Boundary Scan.

[BibT_eX]

[DOI]

Nadime Zacharia

IEEE Trans. Computers, 1998

Design of Phase Shifters for BIST Applications.

[BibT_eX]

[DOI]

Proceedings of the 16th IEEE VLSI Test Symposium (VTS '98), 28 April, 1998

Automated synthesis of large phase shifters for built-in self-test.

[BibT_eX]

[DOI]

Nagesh Tamarapalli

Proceedings of the Proceedings IEEE International Test Conference 1998, 1998

Modular logic built-in self-test for IP cores.

[BibT_eX]

[DOI]

Proceedings of the Proceedings IEEE International Test Conference 1998, 1998

A Fast Sequential Learning Technique for Real Circuits with Application to Enhancing ATPG Performance.

[BibT_eX]

[DOI]

Aiman H. El-Maleh

Proceedings of the 35th Conference on Design Automation, 1998

1997

Arithmetic built-in self-test for DSP cores.

[BibT_eX]

[DOI]

Katarzyna Radecka

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1997

Behavior and testability preservation under the retiming transformation.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1997

Design of Testable Multipliers for Fixed-Width Data Paths.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 1997

Systems On Silicon: Design and Test Challenges.

[BibT_eX]

[DOI]

Proceedings of the 15th IEEE VLSI Test Symposium (VTS'97), 1997

Scan-Encoded Test Pattern Generation for BIST.

[BibT_eX]

[DOI]

Proceedings of the Proceedings IEEE International Test Conference 1997, 1997

Fault Diagnosis in Scan-Based BIST.

[BibT_eX]

[DOI]

Proceedings of the Proceedings IEEE International Test Conference 1997, 1997

Parameterizable Testing Scheme for FIR Filters.

[BibT_eX]

[DOI]

Proceedings of the Proceedings IEEE International Test Conference 1997, 1997

STARBIST: Scan Autocorrelated Random Pattern Generation.

[BibT_eX]

[DOI]

Sybille Hellebrand

Proceedings of the 34st Conference on Design Automation, 1997

1996

A complexity analysis of sequential ATPG.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1996

On Linear Dependencies in Subspaces of LFSR-Generated Sequences.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 1996

Arithmetic Additive Generators of Pseudo-Exhaustive Test Patterns.

[BibT_eX]

[DOI]

Sanjay Gupta

IEEE Trans. Computers, 1996

A self-driven test structure for pseudorandom testing of non-scan sequential circuits.

[BibT_eX]

[DOI]

Fidel Muradali

Proceedings of the 14th IEEE VLSI Test Symposium (VTS'96), April 28, 1996

Hardware-Software Co-Design for Test: It's the Last Straw!

[BibT_eX]

[DOI]

Christos A. Papachristou

John W. Sheppard

Proceedings of the 14th IEEE VLSI Test Symposium (VTS'96), April 28, 1996

Two-Dimensional Test Data Decompressor for Multiple Scan Designs.

[BibT_eX]

[DOI]

Proceedings of the Proceedings IEEE International Test Conference 1996, 1996

Constructive Multi-Phase Test Point Insertion for Scan-Based BIST.

[BibT_eX]

[DOI]

Nagesh Tamarapalli

Proceedings of the Proceedings IEEE International Test Conference 1996, 1996

Multiplicative Window Generators of Pseudo-random Test Vectors.

[BibT_eX]

[DOI]

Proceedings of the 1996 European Design and Test Conference, 1996

1995

Delay-fault testability preservation of the concurrent decomposition and factorization transformations.

[BibT_eX]

[DOI]

Aiman H. El-Maleh

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1995

Built-In Test for Circuits with Scan Based on Reseeding of Multiple-Polynomial Linear Feedback Shift Registers.

[BibT_eX]

[DOI]

Sybille Hellebrand

Steffen Tarnick

Srikanth Venkataraman

Bernard Courtois

IEEE Trans. Computers, 1995

Testability Implications of Performance-Driven Logic Synthesis.

[BibT_eX]

[DOI]

IEEE Des. Test Comput., 1995

Decompression of test data using variable-length seed LFSRs.

[BibT_eX]

[DOI]

Nadime Zacharia

Proceedings of the 13th IEEE VLSI Test Symposium (VTS'95), April 30, 1995

Fault coverage analysis of RAM test algorithms.

[BibT_eX]

[DOI]

Marc D. Riedel

Proceedings of the 13th IEEE VLSI Test Symposium (VTS'95), April 30, 1995

Arithmetic built-in self test for high-level synthesis.

[BibT_eX]

[DOI]

Proceedings of the 13th IEEE VLSI Test Symposium (VTS'95), April 30, 1995

Hierarchical Functional-Fault Simulation for High-Level Synthesis.

[BibT_eX]

[DOI]

Proceedings of the Proceedings IEEE International Test Conference 1995, 1995

On testable multipliers for fixed-width data path architectures.

[BibT_eX]

[DOI]

Proceedings of the 1995 IEEE/ACM International Conference on Computer-Aided Design, 1995

Complexity of sequential ATPG.

[BibT_eX]

[DOI]

Proceedings of the 1995 European Design and Test Conference, 1995

Software Accelerated Functional Fault Simulation for Data-Path Architectures.

[BibT_eX]

[DOI]

Proceedings of the 32st Conference on Design Automation, 1995

On Test Set Preservation of Retimed Circuits.

[BibT_eX]

[DOI]

Proceedings of the 32st Conference on Design Automation, 1995

1994

On necessary and nonconflicting assignments in algorithmic test pattern generation.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1994

Test pattern generation based on arithmetic operations.

[BibT_eX]

[DOI]

Sanjay Gupta

Proceedings of the 1994 IEEE/ACM International Conference on Computer-Aided Design, 1994

1993

Test responses compaction in accumulators with rotate carry adders.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1993

The dynamic reduction of fault simulation.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1993

Recursive Pseudoexhaustive Test Pattern Generation.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 1993

Accumulator-Based Compaction of Test Responses.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 1993

1992

The testability-preserving concurrent decomposition and factorization of Boolean expressions.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1992

BIST of PCB interconnects using boundary-scan architecture.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1992

Empirical Failure Analysis and Validation of Fault Models in CMOS VLSI Circuits.

[BibT_eX]

[DOI]

Ashish Pancholy

Larry J. McNaughton

IEEE Des. Test Comput., 1992

Recent advances in logic synthesis with testability.

[BibT_eX]

[DOI]

Aiman El-Maleh

Proceedings of the 10th IEEE VLSI Test Symposium (VTS'92), 1992

Generation of Vector Patterns Through Reseeding of Multipe-Polynominal Linear Feedback Shift Registers.

[BibT_eX]

[DOI]

Proceedings of the Proceedings IEEE International Test Conference 1992, 1992

1991

On the diagnostic properties of linear feedback shift registers.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1991

Cube-Contained Random Patterns and Their Applications to the Complete Testing of Synthesized Multi-Level Circuits.

[BibT_eX]

[DOI]

Stephen Pateras

Proceedings of the Proceedings IEEE International Test Conference 1991, 1991

Generation of Correlated Random Patterns for the Complete Testing of Synthesized Multi-level Circuits.

[BibT_eX]

[DOI]

Stephen Pateras

Proceedings of the 28th Design Automation Conference, 1991

1990

A method of fault simulation based on stem regions.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1990

Testability preserving transformations in multi-level logic synthesis.

[BibT_eX]

[DOI]

Proceedings of the Proceedings IEEE International Test Conference 1990, 1990

A method to calculate necessary assignments in algorithmic test pattern generation.

[BibT_eX]

[DOI]

Proceedings of the Proceedings IEEE International Test Conference 1990, 1990

Empirical failure analysis and validation of fault models in CMOS VLSI.

[BibT_eX]

[DOI]

Ashish Pancholy

Larry J. McNaughton

Proceedings of the Proceedings IEEE International Test Conference 1990, 1990

A Method for Concurrent Decomposition and Factorization of Boolean Expressions.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 1990

On the Diagnostic Resolution of Signature Analysis.

[BibT_eX]

[DOI]

Babak Salimi

Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 1990

1989

Testing of Glue Logic Interconnects Using Boundary Scan Architecture.

[BibT_eX]

[DOI]

Proceedings of the Proceedings International Test Conference 1989, 1989

1988

A method of fault analysis for test generation and fault diagnosis.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1988

An Algorithmic Branch and Bound Method for PLA Test Pattern Generation.

[BibT_eX]

[DOI]

Markus Robinson

Proceedings of the Proceedings International Test Conference 1988, 1988

Testing and Diagnosis of Interconnects Using Boundary Scan Architecture.

[BibT_eX]

[DOI]

Abu S. M. Hassan

Vinod K. Agarwal

Proceedings of the Proceedings International Test Conference 1988, 1988

Stuck-Open and Transition Fault Testing in CMOS Complex Gates.

[BibT_eX]

[DOI]

Proceedings of the Proceedings International Test Conference 1988, 1988

On Multiple Fault Coverage and Aliasing Probability Measures.

[BibT_eX]

[DOI]

Proceedings of the Proceedings International Test Conference 1988, 1988

A self-reconfiguration scheme for fault-tolerant VLSI processor arrays.

[BibT_eX]

[DOI]

Stephen Pateras

Proceedings of the Computer Design: VLSI in Computers and Processors, 1988

A fault simulation method based on stem regions.

[BibT_eX]

[DOI]

Proceedings of the 1988 IEEE International Conference on Computer-Aided Design, 1988

Parallel PLA fault simulation based on Boolean vector operations.

[BibT_eX]

[DOI]

Eli Chiprout

Markus Robinson

Proceedings of the 1988 IEEE International Conference on Computer-Aided Design, 1988

GEMINI-a logic system for fault diagnosis based on set functions.

[BibT_eX]

[DOI]

Proceedings of the Eighteenth International Symposium on Fault-Tolerant Computing, 1988

A reconvergent fanout analysis for efficient exact fault simulation of combinational circuits.

[BibT_eX]

[DOI]

Proceedings of the Eighteenth International Symposium on Fault-Tolerant Computing, 1988

1987

Testing and Applications of Inverter-Free PLAs.

[BibT_eX]

[DOI]

Vinod K. Agarwal

IEEE Des. Test, 1987

1986

The Influence of Masking Phenomenon on Coverage Capability of Single Fault Test Sets in PLA's.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 1986

1985

Combinatorial Approach to Multiple Contact Faults Coverage in Programmable Logic Arrays.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 1985

Testing Properties and Applications of Inverter-Free PLA's.

[BibT_eX]

Vinod K. Agarwal

Proceedings of the Proceedings International Test Conference 1985, 1985

1984

The detection of small size multiple faults by single fault test sets n programmable logic arrays.

[BibT_eX]

[DOI]

Proceedings of the Fehlertolerierende Rechensysteme, 1984

1980

The Effect of Choosing the Switches for Rearrangements in Switching Networks.

[BibT_eX]

[DOI]

Andrzej Jajszczyk