Hari Ananthan

According to our database, Hari Ananthan authored at least 4 papers between 2004 and 2006.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2006

A fully physical model for leakage distribution under process variations in Nanoscale double-gate CMOS.

Hari Ananthan, Kaushik Roy

Proceedings of the 43rd Design Automation Conference, 2006

2005

Double-gate SOI devices for low-power and high-performance applications.

Kaushik Roy, Hamid Mahmoodi-Meimand, Saibal Mukhopadhyay, Hari Ananthan, Aditya Bansal, Tamer Cakici

Proceedings of the 2005 International Conference on Computer-Aided Design, 2005

2004

FinFET SRAM - Device and Circuit Design Considerations.

Hari Ananthan, Aditya Bansal, Kaushik Roy

Proceedings of the 5th International Symposium on Quality of Electronic Design (ISQED 2004), 2004

Larger-than-vdd forward body bias in sub-0.5V nanoscale CMOS.

Hari Ananthan, Chris H. Kim, Kaushik Roy

Proceedings of the 2004 International Symposium on Low Power Electronics and Design, 2004