Hassan Rabah
Orcid: 0000-0001-6334-3084
According to our database1,
Hassan Rabah
authored at least 55 papers
between 1999 and 2024.
Collaborative distances:
Collaborative distances:
Timeline
Legend:
Book In proceedings Article PhD thesis Dataset OtherLinks
Online presence:
-
on orcid.org
On csauthors.net:
Bibliography
2024
IEEE Trans. Instrum. Meas., 2024
2023
ECG Classification Using an Optimal Temporal Convolutional Network for Remote Health Monitoring.
Sensors, February, 2023
Attention-Enabled Lightweight Neural Network Architecture for Detection of Action Unit Activation.
IEEE Access, 2023
Embedded 1D Convolutional Network based ECG Classification Platform for Remote Health Monitoring.
Proceedings of the 30th IEEE International Conference on Electronics, Circuits and Systems, 2023
Proceedings of the 30th IEEE International Conference on Electronics, Circuits and Systems, 2023
2022
An FPGA-Based Residual Recurrent Neural Network for Real-Time Video Super-Resolution.
IEEE Trans. Circuits Syst. Video Technol., 2022
Proceedings of the 29th IEEE International Conference on Electronics, Circuits and Systems, 2022
An Explainable and Reliable Facial Expression Recognition System for Remote Health Monitoring.
Proceedings of the 29th IEEE International Conference on Electronics, Circuits and Systems, 2022
Proceedings of the 8th International Conference on Control, 2022
2021
A Hybrid Explainable AI Framework Applied to Global and Local Facial Expression Recognition.
Proceedings of the IEEE International Conference on Imaging Systems and Techniques, 2021
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021
2020
Scalable, dynamic and growing hardware self-organizing architecture for real-time vector quantization.
Proceedings of the 27th IEEE International Conference on Electronics, Circuits and Systems, 2020
2018
Efficient reconfigurable regions management method for adaptive and dynamic FPGA based systems.
CoRR, 2018
High performance scalable hardware SOM architecture for real-time vector quantization.
Proceedings of the IEEE International Conference on Image Processing, 2018
2017
Design and Implementation of a Compressed Sensing Encoder: Application to EMG and ECG Wireless Biosensors.
Circuits Syst. Signal Process., 2017
2016
Proceedings of the 2nd International Conference on Advanced Technologies for Signal and Image Processing, 2016
2015
FPGA Implementation of Orthogonal Matching Pursuit for Compressive Sensing Reconstruction.
IEEE Trans. Very Large Scale Integr. Syst., 2015
Compressed Sensing: A Simple Deterministic Measurement Matrix and a Fast Recovery Algorithm.
IEEE Trans. Instrum. Meas., 2015
Fast and efficient signals recovery for deterministic compressive sensing: Applications to biosignals.
Proceedings of the 2015 Conference on Design and Architectures for Signal and Image Processing, 2015
2014
IEEE Trans. Instrum. Meas., 2014
A Novel Framework for the Design of Adaptable Reconfigurable Partitions for the Placement of Variable-sized IP Cores.
IEEE Embed. Syst. Lett., 2014
Proceedings of the 26th International Conference on Microelectronics, 2014
Efficient relocation of variable-sized hardware tasks for FPGA-based adaptive systems.
Proceedings of the 26th International Conference on Microelectronics, 2014
2013
Dynamically reconfigurable entropy coder for multi-standard video adaptation using FaRM.
Microprocess. Microsystems, 2013
Modeling and FPGA implementation of reconfigurable transcoder for real time video adaptation.
Proceedings of the 20th IEEE International Conference on Electronics, 2013
Methodology and reconfigurable architecture for effective placement of variable-size hardware tasks.
Proceedings of the 2013 NASA/ESA Conference on Adaptive Hardware and Systems, 2013
2012
Medical image denoising on field programmable gate array using finite Radon transform.
IET Signal Process., 2012
High level prototyping and FPGA implementation of the orthogonal matching pursuit algorithm.
Proceedings of the 11th International Conference on Information Science, 2012
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012
2011
Proceedings of the 18th IEEE International Conference on Electronics, Circuits and Systems, 2011
Proceedings of the 2011 Conference on Design and Architectures for Signal and Image Processing, 2011
Efficient reconfigurable entropy coder for embedded multi-standards video adaptation.
Proceedings of the IEEE Conference on Computer Vision and Pattern Recognition, 2011
2010
An efficient FPGA-based dynamic partial reconfiguration design flow and environment for image and signal processing IP cores.
Signal Process. Image Commun., 2010
J. Syst. Archit., 2010
Proceedings of the International Conference on Image Processing, 2010
A new FPGA-based dynamic partial reconfiguration design flow and environment for image processing applications.
Proceedings of the 2nd European Workshop on Visual Information Processing, 2010
Dynamically reconfigurable architecture for real time adaptation of H264/AVC-SVC video streams.
Proceedings of the IEEE Conference on Computer Vision and Pattern Recognition, 2010
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2010
2009
An Embedded and Programmable System Based FPGA for Real Time MPEG Stream Buffer Analysis.
IEEE Trans. Circuits Syst. Video Technol., 2009
FPGA-based SoC for transcoding H264/AVC-SVC with low latency and high bitrate entropy coding.
Proceedings of the Annual IEEE International SoC Conference, SoCC 2009, 2009
2008
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2008
Dynamic Slowdown and Partial Reconfiguration to Optimize Energy in FPGA Based Auto-adaptive SoPC.
Proceedings of the 4th IEEE International Symposium on Electronic Design, 2008
2007
Proceedings of the 14th IEEE International Conference on Electronics, 2007
Proceedings of the Second NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2007), 2007
2005
Configurable hardware implementation of a conceptual decoder for a real-time MPEG-2 analysis.
Proceedings of the 2005 International Conference on Field Programmable Logic and Applications (FPL), 2005
2004
SystemC Model of a MPEG-2 DVB-T Bit-Rate Measurement Architecture for FPGA Implementation.
Proceedings of the 15th IEEE International Workshop on Rapid System Prototyping (RSP 2004), 2004
FPGA Implementation of a Novel All Digital PLL Architecture for PCR Related Measurements in DVB-T.
Proceedings of the Field Programmable Logic and Application, 2004
FPGA Implementation of a Novel Architecture for PCR Related Measurements In DVB-T.
Proceedings of the International Conference on Embedded Systems and Applications, 2004
2003
Linear array processors with multiple access modes memory for real-time image processing.
Real Time Imaging, 2003
Temporal partitioning methodology optimizing FPGA resources for dynamically reconfigurable embedded real-time system.
Microprocess. Microsystems, 2003
2002
Proceedings of the Field-Programmable Logic and Applications, 2002
Linear array processors with multiple access modes memory for real-time image processing.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2002, 2002
1999
SIMD/restricted MIMD parallel architecture for Image Processing Based on a New Design of a Multi-mode Access Memory.
Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 1999