Philippe Lorenzini

According to our database, Philippe Lorenzini authored at least 12 papers between 2011 and 2023.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2023

40nm SONOS Embedded Select in Trench Memory.

Radouane Habhab, Vincenzo Della Marca, Pascal Masson, Nadia Miridi, Clement Pribat, Simon Jeannot, Thibault Kempf, Marc Mantelli, Philippe Lorenzini, Jean-Marc Voisin, Arnaud Régnier, Stephan Niel, Francesco La Rosa

Proceedings of the 53rd IEEE European Solid-State Device Research Conference, 2023

2022

Digital-to-analog converters to benchmark the matching performance of a new zero-cost transistor.

Paul Devoge, Hassen Aziza, Philippe Lorenzini, Alexandre Malherbe, Franck Julien, Abderrezak Marzaki, Arnaud Régnier, Stephan Niel

Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

A Schmitt trigger to benchmark the performance of a new zero-cost transistor.

Paul Devoge, Hassen Aziza, Philippe Lorenzini, Pascal Masson, Alexandre Malherbe, Franck Julien, Abderrezak Marzaki, Arnaud Régnier, Stephan Niel

Proceedings of the 29th IEEE International Conference on Electronics, Circuits and Systems, 2022

2021

Circuit-level evaluation of a new zero-cost transistor in an embedded non-volatile memory CMOS technology.

Paul Devoge, Hassen Aziza, Philippe Lorenzini, Franck Julien, Abderrezak Marzaki, Alexandre Malherbe, Marc Mantelli, Thomas Sardin, Sébastien Haendler, Arnaud Régnier, Stephan Niel

Proceedings of the 16th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2021

2016

Study and Reduction of Variability in 28 nm Fully Depleted Silicon on Insulator Technology.

Zhaopeng Wei, Gilles Jacquemod, Philippe Lorenzini, Frédéric Hameau, Emeric de Foucauld, Yves Leduc

J. Low Power Electron., 2016

2014

Low Power 28 nm Fully Depleted Silicon on Insulator 2.45 GHz Phase Locked Loop.

Alexandre Fonseca, Emeric de Foucauld, Philippe Lorenzini, Gilles Jacquemod

J. Low Power Electron., 2014

VCO design in SOI technologies.

Alexandre Fonseca, Gilles Jacquemod, Yves Leduc, Emeric de Foucauld, Philippe Lorenzini

Proceedings of the IEEE 12th International New Circuits and Systems Conference, 2014

2013

Dynamically reconfigurable entropy coder for multi-standard video adaptation using FaRM.

François Duhem, Nicolas Marques, Fabrice Muller, Hassan Rabah, Serge Weber, Philippe Lorenzini

Microprocess. Microsystems, 2013

Design space exploration for partially reconfigurable architectures in real-time systems.

François Duhem, Fabrice Muller, Willy Aubry, Bertrand Le Gal, Daniel Négru, Philippe Lorenzini

J. Syst. Archit., 2013

2012

Reconfiguration time overhead on field programmable gate arrays: reduction and cost model.

François Duhem, Fabrice Muller, Philippe Lorenzini

IET Comput. Digit. Tech., 2012

2011

Methodology for designing partially reconfigurable systems using transaction-level modeling.

François Duhem, Fabrice Muller, Philippe Lorenzini

Proceedings of the 2011 Conference on Design and Architectures for Signal and Image Processing, 2011

FaRM: Fast Reconfiguration Manager for Reducing Reconfiguration Time Overhead on FPGA.

François Duhem, Fabrice Muller, Philippe Lorenzini

Proceedings of the Reconfigurable Computing: Architectures, Tools and Applications, 2011