Hassen Loukil

Orcid: 0000-0002-2028-3517

According to our database1, Hassen Loukil authored at least 18 papers between 2010 and 2023.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

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Bibliography

2023
Hardware implementation and validation of the fast variable block size motion estimation architecture for HEVC Standard.
Multim. Tools Appl., December, 2023

Intelligent Measuring of the Volume Fraction Considering Temperature Changes and Independent Pressure Variations for a Two-Phase Homogeneous Fluid Using an 8-Electrode Sensor and an ANN.
Sensors, August, 2023

2021
A new hardware architecture of the adaptive vector median filter and validation in a hardware/software environment.
Int. J. Circuit Theory Appl., 2021

2020
A Novel Non-DC Biased Intensity Modulated Indoor MIMO-VLC System Using Walsh Precoder.
Wirel. Commun. Mob. Comput., 2020

A novel architecture design for VLSI implementation of integer DCT in HEVC standard.
Multim. Tools Appl., 2020

Hardware-software implementation of HEVC decoder on Zynq.
Multim. Tools Appl., 2020

2019
A Hardware-Efficient Parallel Architecture for HEVC Deblocking Filter.
Proceedings of the 16th International Multi-Conference on Systems, Signals & Devices, 2019

2018
Efficient implementation of HEVC decoder on Zynq SoC platform.
Proceedings of the 4th International Conference on Advanced Technologies for Signal and Image Processing, 2018

HEVC Decoder Analysis on ARM Processor.
Proceedings of the 15th International Multi-Conference on Systems, Signals & Devices, 2018

2017
A Novel Deblocking Filter Architecture for H.264/AVC.
J. Signal Process. Syst., 2017

2016
A new fast motion estimation algorithm using fast mode decision for high-efficiency video coding standard.
J. Real Time Image Process., 2016

An optimized and unified architecture design for H.265/HEVC 1-D inverse core transform.
Proceedings of the International Image Processing, Applications and Systems, 2016

2014
TZSearch pattern search improvement for HEVC motion estimation modules.
Proceedings of the 2014 1st International Conference on Advanced Technologies for Signal and Image Processing (ATSIP), 2014

2013
An efficient architecture VLSI for 4×4 intra prediction in HEVC standard.
Proceedings of the 10th International Multi-Conferences on Systems, Signals & Devices, 2013

Free multiplication integer transformation for the HEVC standard.
Proceedings of the 10th International Multi-Conferences on Systems, Signals & Devices, 2013

2012
FPGA architecture of the LDPS Motion Estimation for H.264/AVC Video Coding.
J. Signal Process. Syst., 2012

2011
HW/SW TQ/IQT design for H.264/AVC.
Proceedings of the 18th IEEE International Conference on Electronics, Circuits and Systems, 2011

2010
FPGA Design of an Intra 16 × 16 Module for H.264/AVC Video Encoder.
Circuits Syst., 2010


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