Hechen Wang
Orcid: 0000-0001-8437-7726
According to our database1,
Hechen Wang
authored at least 17 papers
between 2017 and 2023.
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Bibliography
2023
An Energy-Efficient Bayesian Neural Network Accelerator With CiM and a Time-Interleaved Hadamard Digital GRNG Using 22-nm FinFET.
IEEE J. Solid State Circuits, October, 2023
A Software Requirements Ecosystem: Linking Forum, Issue Tracker, and FAQs for Requirements Management.
IEEE Trans. Software Eng., April, 2023
A Charge Domain SRAM Compute-in-Memory Macro With C-2C Ladder-Based 8-Bit MAC Unit in 22-nm FinFET Process for Edge Inference.
IEEE J. Solid State Circuits, 2023
2022
A 32.2 TOPS/W SRAM Compute-in-Memory Macro Employing a Linear 8-bit C-2C Ladder for Charge Domain Computation in 22nm for Edge Inference.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022
What's Inside a Cluster of Software User Feedback: A Study of Characterisation Methods.
Proceedings of the 30th IEEE International Requirements Engineering Conference, 2022
2021
Proceedings of the 29th IEEE International Requirements Engineering Conference Workshops, 2021
2020
Sub-Sampling Direct RF-to-Digital Converter With 1024-APSK Modulation for High Throughput Polar Receiver.
IEEE J. Solid State Circuits, 2020
A Digital Root Based Modular Reduction Technique for Power Efficient, Fault Tolerance in FPGAs.
Proceedings of the 30th International Conference on Field-Programmable Logic and Applications, 2020
2019
A 3.8 mW Sub-Sampling Direct RF-to-Digital Converter for Polar Receiver Achieving 1.94 Gb/s Data Rate with 1024-APSK Modulation.
Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019
Proceedings of the 27th IEEE International Requirements Engineering Conference, 2019
An 8-bit 80-MS/s Fully Self-Timed SAR ADC with 3/2 Interleaved Comparators and High-Order PVT Stabilized HBT Bandgap Reference.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019
A 280MS/s 12b SAR-Assisted Hybrid ADC with Time Domain Sub-Range Quantizer in 45nm CMOS.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2019
2018
A Reconfigurable Vernier Time-to-Digital Converter With 2-D Spiral Comparator Array and Second-Order ΔΣ Linearization.
IEEE J. Solid State Circuits, 2018
A bidirectional lens-free digital-bits-in/-out 0.57mm<sup>2</sup> terahertz nano-radio in CMOS with 49.3mW Peak power consumption supporting 50cm Internet-of-Things communication.
Proceedings of the 2018 IEEE Custom Integrated Circuits Conference, 2018
2017
An 802.11a/b/g/n Digital Fractional-N PLL With Automatic TDC Linearity Calibration for Spur Cancellation.
IEEE J. Solid State Circuits, 2017
A 14-Bit, 1-ps resolution, two-step ring and 2D Vernier TDC in 130nm CMOS technology.
Proceedings of the 43rd IEEE European Solid State Circuits Conference, 2017
A 330μW 1.25ps 400fs-INL vernier time-to-digital converter with 2D reconfigurable spiral arbiter array and 2<sup>nd</sup>-order ΔΣ linearization.
Proceedings of the 2017 IEEE Custom Integrated Circuits Conference, 2017