Deepak Dasalukunte

Orcid: 0000-0002-5973-0193

According to our database1, Deepak Dasalukunte authored at least 18 papers between 2008 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2023
An Energy-Efficient Bayesian Neural Network Accelerator With CiM and a Time-Interleaved Hadamard Digital GRNG Using 22-nm FinFET.
IEEE J. Solid State Circuits, October, 2023

A Charge Domain SRAM Compute-in-Memory Macro With C-2C Ladder-Based 8-Bit MAC Unit in 22-nm FinFET Process for Edge Inference.
IEEE J. Solid State Circuits, 2023

2022
Low latency communication over commercially available LTE and remote driving.
CoRR, 2022

A 32.2 TOPS/W SRAM Compute-in-Memory Macro Employing a Linear 8-bit C-2C Ladder for Charge Domain Computation in 22nm for Edge Inference.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022

2021
A Vector Processor for Mean Field Bayesian Channel Estimation.
IEEE Trans. Very Large Scale Integr. Syst., 2021

2020
An 802.11ba-Based Wake-Up Radio Receiver With Wi-Fi Transceiver Integration.
IEEE J. Solid State Circuits, 2020

2019
An Ultra-Low Power, Fully Integrated Wake-Up Receiver and Digital Baseband with All-Digital Impairment Correction and -92.4dBm Sensitivity for 802.11ba.
Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019

2017
Adaptive and multi-mode baseband systems for next generation wireless communication.
Proceedings of the 51st Asilomar Conference on Signals, Systems, and Computers, 2017

2013
Hardware Architecture of IOTA Pulse Shaping Filters for Multicarrier Systems.
IEEE Trans. Circuits Syst. I Regul. Pap., 2013

An 0.8-mm<sup>2</sup> 9.6-mW Iterative Decoder for Faster-Than-Nyquist and Orthogonal Signaling Multicarrier Systems in 65-nm CMOS.
IEEE J. Solid State Circuits, 2013

2012
A 0.8 mm<sup>2</sup> 9.6 mW implementation of a multicarrier Faster-than-Nyquist signaling iterative decoder in 65nm CMOS.
Proceedings of the 38th European Solid-State Circuit conference, 2012

2011
Multicarrier Faster-Than-Nyquist Transceivers: Hardware Architecture and Performance Analysis.
IEEE Trans. Circuits Syst. I Regul. Pap., 2011

Complexity analysis of IOTA filter architectures in faster-than-Nyquist multicarrier systems.
Proceedings of the 2011 NORCHIP, Lund, Sweden, November 14-15, 2011, 2011

Improved Memory Architecture for Multicarrier Faster-than-Nyquist Iterative Decoder.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2011

Design and Implementation of Iterative Decoder for Faster-than-Nyquist Signaling Multicarrier Systems.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2011

2010
An Iterative Decoder for Multicarrier Faster-Than-Nyquist Signaling Systems.
Proceedings of IEEE International Conference on Communications, 2010

2009
Transmitter Architecture for Faster-than-Nyquist Signaling Systems.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

2008
An MC-SS Platform for Short-Range Communications in the Personal Network Context.
EURASIP J. Wirel. Commun. Netw., 2008


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