Henrik Hulgaard

According to our database1, Henrik Hulgaard authored at least 22 papers between 1991 and 2003.

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Bibliography

2003
Satisfiability checking using Boolean Expression Diagrams.
Int. J. Softw. Tools Technol. Transf., 2003

2002
Symbolic model checking of timed guarded commands using difference decision diagrams.
J. Log. Algebraic Methods Program., 2002

Boolean Expression Diagrams.
Inf. Comput., 2002

Verification of Hierarchical State/Event Systems using Reusability and Compositionality.
Formal Methods Syst. Des., 2002

Timed Verification of Asynchronous Circuits.
Proceedings of the Concurrency and Hardware Design, Advances in Petri Nets, 2002

2001
Verification of Large State/Event Systems Using Compositionality and Dependency Analysis.
Formal Methods Syst. Des., 2001

2000
Symbolic timing analysis of asynchronous systems.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000

Practical Verification of Embedded Software.
Computer, 2000

1999
Equivalence checking of combinational circuits using Boolean expression diagrams.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999

Fully Symbolic Model Checking of Timed Systems using Difference Decision Diagrams.
Proceedings of the First International Workshop on Symbolic Model Checking, 1999

Equivalence checking of hierarchical combinational circuits.
Proceedings of the 6th IEEE International Conference on Electronics, Circuits and Systems, 1999

Difference Decision Diagrams.
Proceedings of the Computer Science Logic, 13th International Workshop, 1999

Symbolic Time Separation of Events.
Proceedings of the 5th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC '99), 1999

1998
Maximum Time Separation of Events in Cyclic Systems with Linear and Latest Timing Constraints.
Proceedings of the Formal Methods in Computer-Aided Design, 1998

1997
Bounded Delay Timing Analysis of a Class of CSP Programs.
Formal Methods Syst. Des., 1997

Boolean Expression Diagrams (Extended Abstract).
Proceedings of the Proceedings, 12th Annual IEEE Symposium on Logic in Computer Science, Warsaw, Poland, June 29, 1997

1995
An Algorithm for Exact Bounds on the Time Separation of Events in Concurrent Systems.
IEEE Trans. Computers, 1995

Testing asynchronous circuits: A survey.
Integr., 1995

Efficient Timing Analysis of a Class of Petri Nets.
Proceedings of the Computer Aided Verification, 1995

1994
Bounded delay timing analysis of a class of CSP programs with choice.
Proceedings of the International Symposium on Advanced Research in Asynchronous Circuits and Systems, 1994

1993
Practical applications of an efficient time separation of events algorithm.
Proceedings of the 1993 IEEE/ACM International Conference on Computer-Aided Design, 1993

1991
Synthesizing Delay Insensitive Circuits from Verified Programs.
Proceedings of the Research Directions in High-Level Parallel Programming Languages, 1991


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