Steven M. Burns
Orcid: 0000-0003-0248-5403Affiliations:
- Intel Corporation, Hillsboro, OR, USA
- University of Washington, Department of Computer Science and Engineering, Seattle, WA, USA (former)
According to our database1,
Steven M. Burns
authored at least 50 papers
between 1989 and 2023.
Collaborative distances:
Collaborative distances:
Timeline
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Online presence:
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on linkedin.com
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on github.com
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on dl.acm.org
On csauthors.net:
Bibliography
2023
A Generalized Methodology for Well Island Generation and Well-tap Insertion in Analog/Mixed-signal Layouts.
ACM Trans. Design Autom. Electr. Syst., September, 2023
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., September, 2023
Reusing GEMM Hardware for Efficient Execution of Depthwise Separable Convolution on ASIC-Based DNN Accelerators.
Proceedings of the 28th Asia and South Pacific Design Automation Conference, 2023
2022
Proceedings of the ISPD 2022: International Symposium on Physical Design, Virtual Event, Canada, March 27, 2022
Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022
2021
CoRR, 2021
Proceedings of the ISPD '21: International Symposium on Physical Design, 2021
Performance-Aware Common-Centroid Placement and Routing of Transistor Arrays in Analog Circuits.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2021
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021
2020
Proceedings of the ISPD 2020: International Symposium on Physical Design, Taipei, Taiwan, March 29, 2020
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020
GANA: Graph Convolutional Network Based Automated Netlist Annotation for Analog Circuits.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020
2019
Pin Access-Driven Design Rule Clean and DFM Optimized Routing of Standard Cells under Boolean Constraints.
Proceedings of the 2019 International Symposium on Physical Design, 2019
Proceedings of the 56th Annual Design Automation Conference 2019, 2019
2018
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018
A FPGA Accelerator for Real-Time 3D Non-rigid Registration Using Tree Reweighted Message Passing and Dynamic Markov Random Field Generation.
Proceedings of the 28th International Conference on Field Programmable Logic and Applications, 2018
2017
2016
Proceedings of the 43rd ACM/IEEE Annual International Symposium on Computer Architecture, 2016
2015
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2015
Architectural Requirements for Energy Efficient Execution of Graph Analytics Applications.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2015
2013
Proceedings of the International Symposium on Physical Design, 2013
Trace alignment algorithms for offline workload analysis of heterogeneous architectures.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2013
2012
Algorithms for Gate Sizing and Device Parameter Selection for High-Performance Designs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012
Proceedings of the International Symposium on Physical Design, 2012
Proceedings of the 49th Annual Design Automation Conference 2012, 2012
2011
Gate sizing and device technology selection algorithms for high-performance industrial designs.
Proceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design, 2011
Proceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design, 2011
Physical synthesis onto a layout fabric with regular diffusion and polysilicon geometries.
Proceedings of the 48th Design Automation Conference, 2011
2007
Proceedings of the 44th Design Automation Conference, 2007
2002
Lazy transition systems and asynchronous circuit synthesis withrelative timing assumptions.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002
Total power optimization by simultaneous dual-Vt allocation and device sizing in high performance microprocessors.
Proceedings of the 39th Design Automation Conference, 2002
1999
Synthesis of asynchronous control circuits with automatically generated relative timing assumptions.
Proceedings of the 1999 IEEE/ACM International Conference on Computer-Aided Design, 1999
Proceedings of the 36th Conference on Design Automation, 1999
1998
1997
Formal Methods Syst. Des., 1997
1996
Proceedings of the 2nd International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC '96), 1996
1995
IEEE Trans. Very Large Scale Integr. Syst., 1995
An Algorithm for Exact Bounds on the Time Separation of Events in Concurrent Systems.
IEEE Trans. Computers, 1995
Proceedings of the Computer Aided Verification, 1995
1994
An FPGA for Implementing Asynchronous Circuits.
IEEE Des. Test Comput., 1994
Proceedings of the International Symposium on Advanced Research in Asynchronous Circuits and Systems, 1994
1993
Proceedings of the 1993 IEEE/ACM International Conference on Computer-Aided Design, 1993
1992
Proceedings of the Field-Programmable Gate Arrays: Architectures and Tools for Rapid Prototyping, Second International Workshop on Field-Programmable Logic and Applications, Vienna, Austria, August 31, 1992
1991
1989
SIGARCH Comput. Archit. News, 1989