Steven M. Burns

According to our database1, Steven M. Burns authored at least 38 papers between 1989 and 2021.

Collaborative distances:
  • Dijkstra number2 of two.
  • Erdős number3 of four.

Timeline

Legend:

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Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2021
ALIGN: A System for Automating Analog Layout.
IEEE Des. Test, 2021

Machine Learning Techniques in Analog Layout Automation.
Proceedings of the ISPD '21: International Symposium on Physical Design, 2021

Common-Centroid Layouts for Analog Circuits: Advantages and Limitations.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

2020
Learning from Experience: Applying ML to Analog Circuit Design.
Proceedings of the ISPD 2020: International Symposium on Physical Design, Taipei, Taiwan, March 29, 2020

The ALIGN Open-Source Analog Layout Generator: v1.0 and Beyond (Invited talk).
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020

GANA: Graph Convolutional Network Based Automated Netlist Annotation for Analog Circuits.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

2019
ALIGN: Open-Source Analog Layout Automation from the Ground Up.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019

2018
A Template-Based Design Methodology for Graph-Parallel Hardware Accelerators.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

A FPGA Accelerator for Real-Time 3D Non-rigid Registration Using Tree Reweighted Message Passing and Dynamic Markov Random Field Generation.
Proceedings of the 28th International Conference on Field Programmable Logic and Applications, 2018

2017
Graph Analytics Accelerators for Cognitive Systems.
IEEE Micro, 2017

2016
Energy Efficient Architecture for Graph Analytics Accelerators.
Proceedings of the 43rd ACM/IEEE Annual International Symposium on Computer Architecture, 2016

2015
Wavelet-Based Trace Alignment Algorithms for Heterogeneous Architectures.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015

Hardware Accelerator Design for Data Centers.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2015

Architectural Requirements for Energy Efficient Execution of Graph Analytics Applications.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2015

2013
An improved benchmark suite for the ISPD-2013 discrete cell sizing contest.
Proceedings of the International Symposium on Physical Design, 2013

Trace alignment algorithms for offline workload analysis of heterogeneous architectures.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2013

2012
Algorithms for Gate Sizing and Device Parameter Selection for High-Performance Designs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012

The ISPD-2012 discrete cell sizing contest and benchmark suite.
Proceedings of the International Symposium on Physical Design, 2012

2011
Gate sizing and device technology selection algorithms for high-performance industrial designs.
Proceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design, 2011

A trace compression algorithm targeting power estimation of long benchmarks.
Proceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design, 2011

2007
Comparative Analysis of Conventional and Statistical Design Techniques.
Proceedings of the 44th Design Automation Conference, 2007

2002
Lazy transition systems and asynchronous circuit synthesis withrelative timing assumptions.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002

Total power optimization by simultaneous dual-Vt allocation and device sizing in high performance microprocessors.
Proceedings of the 39th Design Automation Conference, 2002

1999
Synthesis of asynchronous control circuits with automatically generated relative timing assumptions.
Proceedings of the 1999 IEEE/ACM International Conference on Computer-Aided Design, 1999

CAD Directions for High Performance Asynchronous Circuits.
Proceedings of the 36th Conference on Design Automation, 1999

1997
Bounded Delay Timing Analysis of a Class of CSP Programs.
Formal Methods Syst. Des., 1997

1996
General conditions for the decomposition of state holding elements.
Proceedings of the 2nd International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC '96), 1996

1995
Placement and routing tools for the Triptych FPGA.
IEEE Trans. Very Large Scale Integr. Syst., 1995

The Triptych FPGA architecture.
IEEE Trans. Very Large Scale Integr. Syst., 1995

An Algorithm for Exact Bounds on the Time Separation of Events in Concurrent Systems.
IEEE Trans. Computers, 1995

Testing asynchronous circuits: A survey.
Integr., 1995

Efficient Timing Analysis of a Class of Petri Nets.
Proceedings of the Computer Aided Verification, 1995

1994
An FPGA for Implementing Asynchronous Circuits.
IEEE Des. Test Comput., 1994

Bounded delay timing analysis of a class of CSP programs with choice.
Proceedings of the International Symposium on Advanced Research in Asynchronous Circuits and Systems, 1994

1993
Practical applications of an efficient time separation of events algorithm.
Proceedings of the 1993 IEEE/ACM International Conference on Computer-Aided Design, 1993

1992
MONTAGNE: An FPL for Synchronous and Asynchronous Circuits.
Proceedings of the Field-Programmable Gate Arrays: Architectures and Tools for Rapid Prototyping, Second International Workshop on Field-Programmable Logic and Applications, Vienna, Austria, August 31, 1992

1989
The design of an asynchronous microprocessor.
SIGARCH Comput. Archit. News, 1989

The first asynchronous microprocessor: the test results.
SIGARCH Comput. Archit. News, 1989


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